Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 132
2. Power consumption. For some variants of circuits we have been able to measure the
relative power consumption of placed and unplaced designs and compare them. Once
again we would hope that manually placed designs would have lower power consump-
tion, however this may differ from circuit to circuit.
3. Place and route time. The time taken to place and route a circuit is an important
part of the overall hardware compilation time, particularly for dynamic specialisation
applications where it is necessary to generate circuits very quickly. This is measured
by the Xilinx synthesis tools running on an Intel dual Pentium 4 Xeon 2.6Ghz PC with
4GB of RAM.
4. Logic area. The logic area used by circuits will be measured as the number of slices
required on the Virtex-II.
6.2 Adder Tree
The simplest circuits we analyse are pipelined and unpipelined binary adder trees.
6.2.1 Ripple Adder
Binary ripple adders can be laid out quite densely on the Virtex-II architecture, using a single
slice to implement the addition (and pipeline delay, if desirable) of two bits. This is because
the architecture of each slice (Figure 2.2, page 11) is such that two full-adder circuits can be
implemented in a single slice, using both function generators and the carry chain.
The Virtex slice architecture contains specialised carry logic designed to create fast carry
chains. A Virtex full adder can be built by using the 4-input look-up table as an xor function
which is then connected to the muxcy carry multiplexer to generate the carry out signal and
xorcy logic to generate the sum result signal (which can then be registered if desired). This
arrangement is depicted in Figure 6.1 and the Quartz code which generates this arrangement
is shown in Figure 6.2. This description exploits the geometric interpretation of Quartz block
domains and ranges to use the cout signal in the domain to indicate that it is connected to
the top side of the block and cin in the range to indicate it is on the bottom of the block.