Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 6. LAYOUT CASE STUDIES 131
a flattened, placed netlist in VHDL format. This flattened VHDL instantiates architecture
primitives and is enclosed in a hand-coded VHDL testbench for synthesis using the Xilinx ISE
software. The testbench has been used to carry out the following functions as appropriate:
1. Clock division. Where the power consumption of circuits has been measured a simple
clock divider circuit has been used to ensure that all circuits are run within their
maximum clock frequency.
2. Generating input data. Linear Feedback Shift Register Counters [3] are used to provide
pseudo-random input data to designs when necessary.
3. Provision of suitable interface registers.
4. XORing of outputs to a single chip pin.
Outputs were XORed together when it was desired to investigate the power consumption of
the circuitry on a chip to the minimise the influence of I/O power. It is necessary to connect
a single output pin to prevent the entire circuit being optimised away by the synthesis tools.
Power consumption has been measured from a Celoxica RC200 development board, equipped
with an XC2V1000 FPGA. This is a complex development board and the board power con-
sumption dwarfs that of the FPGA itself, thus we have measured the quiescent power of
the board (when the FPGA is programmed to be empty) and deducted this from our power
measurements. Power consumption itself was measured by monitoring the current drawn by
the board at its operating voltage of 12V.
We use four metrics to evaluate our designs:
1. Maximum clock frequency. This is an important measure of the performance of the
generated circuit, indicating how fast it can be run and thus how fast it can process
data. We would hope that manually placed designs would have higher maximum clock
frequencies than automatically placed ones, however previous results have shown that
this is not always the case [77]. While placed designs often outperform unplaced designs
very significantly, some types of design do not. Maximum clock frequency is not the
only characteristic of circuits we are interested in and a placed design may still be
preferable to an unplaced one if it outperforms on one of our other metrics.