Verification of Parameterised FPGA Circuit Descriptions with Layout ...

Chapter 6
Layout Case Studies
In this chapter we demonstrate the use of our layout framework by describing some full
circuits and comparing the performance and compilation times for versions with and without
placement. Section 6.1 outlines our basic approach to collecting results. In Section 6.2 we
describe pipelined and unpipelined binary trees of ripple adders. Section 6.3 gives the Quartz
design and results for a simple median filter, while Section 6.4 describes a butterfly network
of 2-sorters and introduces the low-level register pipelining combinator. Section 6.5 describes
and analyses a binomial filter circuit. Section 6.6 introduces a new class of n-dimensional
combinators and shows how the 3D version can be used to describe a matrix multiplier
with an implicit 2D layout interpretation. Section 6.7 evaluates our results and Section 6.8
summarises this chapter.
6.1 Approach
In this chapter we describe a variety of different circuits with layout information, verify their
layouts and evaluate the performance of the resulting circuit with and without the placement
constraints. Designs were synthesised for a Xilinx Virtex-II FPGA so that the required logic
resources, maximum operating frequency and power consumption could be measured.
Designs are expressed in Quartz and compiled using the Quartz compiler with layout gen-
eration (Chapter 3) into Pebble 5. The Pebble 5 compiler [66] is then used to produce
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