Verification of Parameterised FPGA Circuit Descriptions with Layout ...
Verification of Parameterised FPGA Circuit Descriptions with Layout ... Verification of Parameterised FPGA Circuit Descriptions with Layout ...
CHAPTER 1. INTRODUCTION 4 1.2 Contributions The contributions of this thesis are: 1. A framework supporting the addition of generic layout information to parameterised FPGA libraries described in the Quartz language. We show how these circuit de- scriptions can be compiled onto FPGAs and describe how they can be translated into parameterised library descriptions in the Pebble hardware description language and structural VHDL. We give all Quartz circuit descriptions composed using standard li- brary combinators a basic layout interpretation, which is often already optimal, and also allow descriptions to be annotated to change the generated layout while maintaining the same function through the use of the overloaded combinator blocks. (Chapter 3) 2. We provide a specification of layout correctness and construct an environment based on higher-order logic to allow the verification of the manual layouts specified for Quartz combinators and for full circuits. We prove a range of useful properties about common circuit layout expressions which we use to automate the verification of layouts for new combinators or circuits using the Isabelle theorem prover. (Chapter 4) 3. We develop and verify a range of placed combinator libraries for common structures such as rows, columns, grids, trees and less regular examples such as the pathological example shown in Figure 1.1 and a square-element interface configuration. We achieve high levels of automation in the verification of these combinator layouts, with many proofs completed without any human intervention and others requiring only minimal user involvement. We show that the verification framework can not only establish correctness of valid layouts but also highlight counter-examples where layouts are not correct. (Chapter 4) 4. We introduce distributed specialisation, where HDL-level specialisation of circuits when one or more inputs are known can be achieved without centralised control. Distributed specialisation allows circuits to be specialised in order to produce higher-performance variants at the HDL-level, eliminating or reducing the need for slow low-level opti- misation of circuits in time-critical dynamic specialisation applications. Distributed specialisation also makes formal verification of the specialisation process much sim-
CHAPTER 1. INTRODUCTION 5 pler, allowing the correctness of all specialised circuits to be established by proving their equivalence to the original general circuit. We show that our layout framework supports distributed specialisation and can be used to achieve design compaction dur- ing specialisation of parameterised circuits, in contrast to more conventional low-level approaches which eliminate unnecessary logic but do not compact the circuit. Speciali- sation with compaction reduces the area on-chip that must be allocated to a circuit and we demonstrate that it improves performance for a simple parallel multiplier design. (Chapter 5) 5. We describe and verify the layout for five example circuits, including a median filter, butterfly network and a matrix multiplier described using a new class of n-dimensional combinators, and investigate the benefits of using user-specified placement constraints during synthesis. We show that manually placed designs can be placed a d routed faster and often have higher performance and lower power consumption while requiring less logic area on a Xilinx Virtex-II device. Improvements of up to 80% in maximum clock frequency and a 61% reduction in area are observed. (Chapter 6) 1.3 Organisation The remainder of this thesis is organised as follows: Chapter 2 presents relevant background information and related work. Chapter 3 introduces the layout description framework and illustrates how circuit descriptions with layout information can be compiled. Chapter 4 de- tails the layout verification environment and gives details of some key proofs. Chapter 5 introduces distributed specialisation and demonstrates the use of the layout framework to produce specialised circuits. Chapter 6 describes the construction, verification and perfor- mance of some example circuits. Chapter 7 evaluates this work, draws conclusions and presents recommendations for future research. Appendix A gives the full grammar of the extended Quartz language. Appendix B gives the definitions and proofs in the verification environment for Quartz circuit layouts and Appendix C gives example proofs for a variety of library combinators. Appendix D contains some of the proofs for the layout correctness of the circuit examples in Chapter 6.
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CHAPTER 1. INTRODUCTION 4<br />
1.2 Contributions<br />
The contributions <strong>of</strong> this thesis are:<br />
1. A framework supporting the addition <strong>of</strong> generic layout information to parameterised<br />
<strong>FPGA</strong> libraries described in the Quartz language. We show how these circuit de-<br />
scriptions can be compiled onto <strong>FPGA</strong>s and describe how they can be translated into<br />
parameterised library descriptions in the Pebble hardware description language and<br />
structural VHDL. We give all Quartz circuit descriptions composed using standard li-<br />
brary combinators a basic layout interpretation, which is <strong>of</strong>ten already optimal, and also<br />
allow descriptions to be annotated to change the generated layout while maintaining<br />
the same function through the use <strong>of</strong> the overloaded combinator blocks. (Chapter 3)<br />
2. We provide a specification <strong>of</strong> layout correctness and construct an environment based on<br />
higher-order logic to allow the verification <strong>of</strong> the manual layouts specified for Quartz<br />
combinators and for full circuits. We prove a range <strong>of</strong> useful properties about common<br />
circuit layout expressions which we use to automate the verification <strong>of</strong> layouts for new<br />
combinators or circuits using the Isabelle theorem prover. (Chapter 4)<br />
3. We develop and verify a range <strong>of</strong> placed combinator libraries for common structures<br />
such as rows, columns, grids, trees and less regular examples such as the pathological<br />
example shown in Figure 1.1 and a square-element interface configuration. We achieve<br />
high levels <strong>of</strong> automation in the verification <strong>of</strong> these combinator layouts, <strong>with</strong> many<br />
pro<strong>of</strong>s completed <strong>with</strong>out any human intervention and others requiring only minimal<br />
user involvement. We show that the verification framework can not only establish<br />
correctness <strong>of</strong> valid layouts but also highlight counter-examples where layouts are not<br />
correct. (Chapter 4)<br />
4. We introduce distributed specialisation, where HDL-level specialisation <strong>of</strong> circuits when<br />
one or more inputs are known can be achieved <strong>with</strong>out centralised control. Distributed<br />
specialisation allows circuits to be specialised in order to produce higher-performance<br />
variants at the HDL-level, eliminating or reducing the need for slow low-level opti-<br />
misation <strong>of</strong> circuits in time-critical dynamic specialisation applications. Distributed<br />
specialisation also makes formal verification <strong>of</strong> the specialisation process much sim-
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