Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 5. SPECIALISATION 124
Yin
ACCin
Qin
y
x
Figure 5.11: Virtex-II cell configuration to create a parallel multiplier
ACCout
Yin
Pout
SLICE LOGIC
Xin
Xout
Qin Pin
Xin
(a) Standard cell design
Yout
SUMout
Yin
Pout
ACCin
Pin
ACCout
Qin
SUMout
(b) Specialised X=0
Figure 5.12: Functional cells for parallel multiplier
block multcell ((wire acc in, wire y in), (wire acc out, wire p out, wire x out)) ∼
((wire q in, wire p in, wire x in), (wire sum out, wire y out))
attributes { height = 1. width = 1. }{
wire xored sig.
y out = y in.
x out = x in.
acc out = acc in.
(x in, y in, q in) ; mult lut ; xored sig at (0,0).
(p in, xored sig) ; xorcy ; sum out at (0,0).
((x in, y in), p in) ; fst mult and ;muxcy xored sig ;p out at (0,0).
}
Figure 5.13: Quartz description of the multiplier cell
Yout
SUMout