Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 5. SPECIALISATION 123
a fast carry chain designed to support the generation of fast adders and multipliers. Each
half-slice also contains a mult and component which allows two functional cells implementing
multiplication to be described within a single slice. Figure 5.11 illustrates how a half-slice
can be configured to form part of the functional cell of a multiplier.
At first glance this is an inefficient way of implementing the functional cell, since the x · y
logical and operation is computed twice. However this is not actually the case since the area
within the dotted boundary is implemented using the slice look-up table. The performance
and area required by the look-up table is independent of the actual logic function it is used
to implement and the intermediate x · y signal does not actually exist, so can not be used as
an input to the top multiplexer.
The lower and gate is the slice mult and component which is specifically available for carrying
out this operation and can only be connected to the lower two inputs of the look-up table.
The second exclusive-or operation and the multiplexer are also available already as dedicated
devices within the slice so do not require any additional resources that are not already in
existence.
This slice logic can be combined with a wiring arrangement to form a cell suitable for com-
position into a grid. Figure 5.12(a) shows the wiring within a multiplier cell and how it is
connected to the slice circuitry. The ACCin and ACCout signals provide a diagonal connec-
tion between the SUMout output of the cell to the left and the Qin input of the cell above.
X and Y signals are routed through the cell as well as being connected to the slice logic and
the output signals are connected to the cells above and to the right. Figure 5.13 shows the
Quartz description of the multiplier cell.
This cell design can be composed into a grid, describing a multiplier with a y input on the
left and x input on the bottom. The multiplication results are output on the right side and
the top side. When multiplying an n bit number by an m bit number the lower n bits of
the result will be output on the right and the upper m bits will be available in carry-save
representation on the top connections. An additional adder circuit must be connected to the
top connections to produce a full m+n bit output. Figure 5.14 shows the Quartz description
for an n-bit by n-bit multiplier, where only the first n bits of the output are utilised. This
circuit is similar to one derived formally using the T-Ruby system [68], although ours is