Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 5. SPECIALISATION 122
irregular positions can be eliminated using primitive-level specialisation.
High-level specialisation can fit our definition of distributed specialising - blocks operating
independently without centralised control. In some cases it may be desirable to provide
explicit control over the kind of specialisation engaged in and this can be done by adding extra
parameters. The Quartz overloading mechanism can be used to overload a parameterised
block with a non-parameterised one which instantiates the self-specialising block with a
default set of parameters – the same method we used in Section 3.6 to give blocks multiple
layout interpretations.
5.5 Specialising a Multiplier
We will demonstrate high level specialisation with a simple example: a parallel multiplier
circuit. Since one of the main advantages of specialising designs in Quartz rather than using
synthesis tool optimisations is that we are able to specialise and compact placed designs
we will take this opportunity to evaluate whether any performance benefit is gained from
compaction.
5.5.1 Parallel Multiplier Implementation
Before we can specialise a multiplier circuit it is necessary to describe a multiplier circuit in
Quartz. Since we are interested in evaluating the real performance of the specialised circuit,
we will design a multiplier for a real FPGA architecture - Xilinx Virtex-II.
A parallel multiplier operates using a shift-add methodology that is similar to the way binary
multiplication is performed on paper. A multiplier performing the operation x × y can
be described as a grid-shaped circuit with x values flowing vertically and y values flowing
horizontally. Each functional cell must perform a the multiplication operation for one bit
of x and one bit of y, producing sum and carry outputs in a similar way to a ripple adder,
except that these outputs will be connected to additional processing cells with only the final
stage producing an output.
The Virtex-II architecture contains specific components within each half-slice to implement