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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 5. SPECIALISATION 121<br />

Buffer/Queue<br />

R<br />

(a) General circuit<br />

R<br />

Buffer/Queue<br />

(b) Specialised<br />

R<br />

Buffer/Queue<br />

Additional Control Logic<br />

R R<br />

Additional Control Logic<br />

(c) Parallelised<br />

Figure 5.10: Space freed by specialisation can be used to further parallelise a circuit<br />

clock frequency but hopefully <strong>with</strong> reduced power consumption due to the reduction in glitch<br />

propagation [85].<br />

Alternatively, if the logic resources required to carry out a computation can be reduced<br />

but the space allocated on the device remains the same then the freed space can be used<br />

for accelerating the computation in other ways. It could even be used to duplicate the<br />

computational unit, increasing throughput if tasks are switched between processors rather<br />

than queueing for a single processor, as illustrated in Figure 5.10. In this diagram, the dotted<br />

box indicates the logic area allocated to the computation, which can be used to implement<br />

either a general processor, a single specialised processor and some unused logic, or multiple<br />

specialised processors <strong>with</strong> additional control.<br />

This kind <strong>of</strong> specialisation is not mere constant propagation and requires a higher-level <strong>of</strong><br />

designer involvement. <strong>Circuit</strong> designers can program library blocks to exhibit this kind <strong>of</strong><br />

specialisation behaviour, using Quartz conditionals extended <strong>with</strong> block size constructs to<br />

identify the size <strong>of</strong> specialised components. This means that a block to implement the system<br />

in Figure 5.10 could generate any number <strong>of</strong> additional copies <strong>of</strong> the computational block<br />

depending on the ratio between the size <strong>of</strong> Rgen and Rspec.<br />

High-level specialisation can also be used to perform constant propagation on a macro-level,<br />

eliminating the need to process the specialisation individually for each primitive block. This<br />

means that the specialisation process can be run more quickly, important for dynamic spe-<br />

cialisation applications where it is necessary to produce a new circuit quickly at run-time.<br />

High-level and primitive-level specialisation can be combined in descriptions so that large<br />

contiguous collections <strong>of</strong> blocks can be eliminated at the high level while individual blocks in

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