Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 5. SPECIALISATION 120
block or2 (data a, data b) ∼ (data c) {
if (a = Known a2) {
if a2 { c = Known true. }else { c = b. } .
} else if (b = Known b2) {
if b2 { c = Known true. }else { c = Known false. }.
} else
(Wire a, Wire b) ; or2 ; (Wire c).
} .
}
Figure 5.9: Distributed specialisation for an or2 block with a better type system
5.4 High Level Specialisation
Primitive-level specialisation with clever components that can eliminate individual gates is
a useful process however it is not a total solution to all possible specialisation requirements.
A higher level approach to specialisation, writing specialisation code for larger blocks such
as library elements, also has a significant role to play.
An important consideration is that constant folding, while one of the most useful optimi-
sations to carry out when specialising circuits with an aim to reduce their area or improve
performance, is not the only specialisation procedure we might wish to apply. There are
many reasons we might wish to specialise a design, for example:
1. To eliminate unnecessary logic in order to free space on the device for other function-
ality, or to reduce the circuit’s power consumption.
2. To increase the maximum clock frequency and run the circuit at a higher speed.
3. To eliminate unnecessary computation from the critical path of a pipelined design,
reducing the overall latency.
4. To free space, allowing it to be used to further parallelise the computation.
Items 3 & 4 are particularly interesting. If the initial stages of a pipelined computation could
be eliminated by pre-computation of some of the inputs then the resulting circuit’s latency
could be reduced. If the circuit is required to have a specific latency then this “latency slack”
can be used to introduce additional pipelining in the later stages. This could then allow the
design to run at a higher clock frequency overall, or the design could be run at the same