Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 1. INTRODUCTION 3
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Figure 1.1: An irregular grid such as this one is impossible to describe using purely beside
and below relative placement.
Run-time reconfiguration is a growing area of interest as designers seek to make better use of
the reconfigurable nature of FPGAs to improve performance, particularly since FPGAs are
otherwise slower and more power-hungry than ASICs.
Placement information can be specified within hardware description languages by giving
explicit co-ordinates for each component, however this approach is tedious and error prone.
The potential for errors is particularly significant for parameterised libraries since designs
which have painstakingly been established as functionally correct may still fail to synthesise
properly for some parameter values if these particular parameterisations produce an invalid
layout – for example, one where more than one component is placed at the same location or
components are placed outside the area on the chip allocated to the library design.
The use of relative placement information, placing components beside or below one another,
has been proposed for simplifying the process of laying out circuits and reducing the potential
for errors. Errors can not be totally eliminated unless explicit placement is disallowed entirely
and beside/below placement alone is utilised, however this approach is too restrictive to
permit the description of all possible desirable circuit layouts. For example, it is impossible to
describe the layout of components shown in Figure 1.1 using only beside and below placement
directives.
The objective of this work is to create a framework allowing the clear and efficient description
of parameterised circuit descriptions with layout information and which provides a formal
assurance of correctness for layouts.
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