Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 5. SPECIALISATION 118
block or2 (bool a, wire b) ∼ (wire c) attributes { width = 0. height = 0. }
→ if a { c = true. } else { c = b. } .
block or2 (wire a, bool b) ∼ (wire c)
→ (b, a) ; or2 ; c.
Figure 5.8: Distributed specialisation for an or2 block
the dynamic input or statically assign it to some value, depending on the value of the static
input.
For or2, c is connected to b if a is false, and connected to ground otherwise. Because c is
connected to a wire in one branch of the conditional it must itself have a wire type since it
is not possible to assign wire values to any other type. The assignment c = true used in
the other branch uses the overloaded signal connection operator, which allows static boolean
values to be assigned to wires.
This block correctly specialises itself, however it does not allow a propagation of the constant
value. If a is true, the more optimal solution is to produce a boolean output c assigned with
the value true. This would then allow blocks connected to the c output of or2 to properly
specialise themselves, whereas with this block description other blocks assume that the value
of c is unknown.
5.3.2 Modified Type System
To achieve proper propagation of the constant, c would need to be typed as a boolean if a
is true and as a wire otherwise. This is impossible in a statically typed language like Quartz
where types are determined by an inference process prior to the program executing.
This problem also occurs at the combinator level. When the col combinator is used to
connect together multiple fadd blocks it requires that the fadd block has a type of the form
(α, β) ∼ (β, γ) - that is that the top and bottom connections must have the same type so they
can be connected together. This means that it is not possible for the carry signal moving up
the column to alternate between bool and wire types, depending on whether the carry value is
known. Nor is it possible to take account of the fact that, in our ripple adder implementation,
the initial carry-in input is always zero and use this to simplify the first full adder.