Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 5. SPECIALISATION 116
b
a
cout
cin
Figure 5.6: Full adder cell
These layout theorems can be proved for each self-specialising block and then these proofs
combined to verify the size correctness of an entire circuit. This once again neatly decomposes
a potentially large verification task into many small and easy parts. For example, for the
xor2 gate in Figure 5.4 the width correctness theorem can be stated and proved easily:
∀ a b c. Width xor2spec a b c ≤ Width xor2gen a b c
⇒ ∀ a b c. if(a, 1, 0) ≤ 1
⇒ 1 ≤ 1 ∧ 0 ≤ 1 ⇒ True
5.3 Optimal Distributed Specialisation
Reviewing the effectiveness of our self-specialising blocks on a real circuit we discover that it
is necessary to address some shortcomings with the basic approach.
5.3.1 Specialising a Ripple Adder
We will demonstrate distributed specialisation in Quartz using a simple ripple adder circuit.
This is composed of full adder cells as shown in Figure 5.6 and described in Quartz as shown
in Figure 5.7. The full adder is implemented using two xor gates and a multiplexer, which is
described separately using two 2-input and gates, an or and an inverter. This description is
not designed for any particular target architecture however, and what matters is the effect
on this circuit of specialising it.
As can be seen in Figure 5.7 the full-adder block accepts only hardware wires for inputs cin
ans