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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 5. SPECIALISATION 115<br />

constdefs (∗ Semantics for hardware primitives ∗)<br />

and2 :: "wire⇒ wire⇒ wire⇒ bool"<br />

"and2 ≡ (λ a b c. c = (a ∧ b))"<br />

inv :: "wire⇒ wire⇒ bool"<br />

"inv ≡ (λ a b. b = (˜ a))"<br />

xor2 :: "wire⇒ wire⇒ wire⇒ bool"<br />

"xor2 ≡ (λ a b c. c = (a ∧ (˜ b) | b ∧ (˜a)))"<br />

constdefs (∗ Semantics for partial specialisation blocks ∗)<br />

and2’ :: "bool⇒ wire⇒ wire⇒ bool"<br />

"and2’ ≡ (λ a b c. if a then (c = b) else (c = False))"<br />

xor2’ :: "bool⇒ wire⇒ wire⇒ bool"<br />

"xor2’ ≡ (λ a b c. if a then (inv b c) else (c = b))"<br />

(∗ Correctness theorems for specialised blocks ∗)<br />

theorem and2 spec: "Îabc. and2 a b c = and2’ a b c"<br />

by (simp add: and2 def and2’ def)<br />

theorem xor2 spec: "Îabc. xor2 a b c = xor2’ a b c"<br />

by (simp add: xor2 def xor2’ def inv def)<br />

Figure 5.5: Functional verification <strong>of</strong> distributed specialisation <strong>of</strong> and2 and xor2<br />

semantic function Bβ (Figure 4.8, page 81).<br />

This is actually a rather simpler verification model than would be desired, since the wire<br />

type is simply a synonym for bool and thus there is no need for explicit reference to the types<br />

<strong>of</strong> the input/output signals - nevertheless it suitably demonstrates the concept. The two<br />

theorems demonstrating the equivalence <strong>of</strong> the blocks are proved by using just the simplifier<br />

and expanding the block definitions.<br />

Functional verification is only one side <strong>of</strong> the verification task: it is also vital to verify the<br />

correctness <strong>of</strong> the layout <strong>of</strong> a specialised circuit. This can be done using the layout verification<br />

framework we described in Chapter 4. When specialising designs it is useful to state and<br />

prove a particular additional correctness theorem <strong>of</strong> the form:<br />

∀sigs. Width cctspec sigs ≤ Widthcctgen sigs ∧ Heightcctspec sigs ≤ Heightcctgen sigs<br />

In fact, this theorem should be phrased so it is only universally quantified over dynamic<br />

parameters. Parameters which genuinely affect the size <strong>of</strong> the circuit and are not expected to<br />

vary at run-time (such as the bit-width <strong>of</strong> a ripple adder) can not be included in such pro<strong>of</strong>s<br />

since it would clearly render the theorem unprovable.

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