Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 5. SPECIALISATION 113
circuit, rather than just eliminating some logic internally while maintaining the same overall
bounding box. This means that the free logic resources on the FPGA can be used more
efficiently. It also minimises wire lengths by moving components that would otherwise be
joined by long wires to be adjacent to each other.
The second advantage of distributed specialisation is that, because it is conducted at a high-
level, it should be able to be processed much faster than low level constant propagation. This
is aided because, due to the overloading mechanism only selecting specialising blocks if at
least one input is static, constant propagation only needs to be analysed through the parts
of the circuit where it can actually have an effect.
In addition, distributed specialisation does not just have to take place at the primitive level.
Designers who write hardware library blocks can also provide blocks with specialisation code
which could perform high level optimisations rather than using the code in the lower level
circuit blocks. For example, this means that a grid shaped circuit where entire rows are
expected to be eliminated can be specialised at the row level rather than processing each
row element individually. We discuss in the advantages of high level specialisation further in
Section 5.4.
Speed is an important factor in any mechanism that is intended for use in dynamic specialisa-
tion applications where it is imperative to minimise the time taken to generate a new FPGA
bitstream. Using distributed specialisation with the Quartz layout framework it is possible
to describe constant propagation, mapping (by using only primitive hardware components
in descriptions) and placement all within the high-level description leaving only routing and
bitstream generation to be completed on the system output before it can be used to configure
a device.
The third advantage of distributed specialisation is that it provides a clear and modular
framework with which to verify the specialisation procedure and thus, by extension, the
correctness of all specialised circuits produced.