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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 5. SPECIALISATION 112<br />

// Hardware primitive<br />

block xor2 (wire a, wire b) ∼ (wire c) attributes { height = 1. width = 1. }{ }<br />

// Specialising when both inputs are known<br />

block xor2 (bool a, bool b) ∼ (bool c) attributes { width = 0. height = 0. }<br />

→ c = (a xor b).<br />

// Specialising when one input is known<br />

block xor2 (bool a, wire b) ∼ (wire c)<br />

attributes { width = if (a,1,0). height = if (a,1,0). }<br />

→ if a { b ; inv ; c. } else { c = b. } .<br />

block xor2 (wire a, bool b) ∼ (wire c)<br />

→ (b, a) ; xor2 ; c.<br />

5.2.2 Benefits<br />

Figure 5.4: Distributed specialisation <strong>of</strong> an xor2 block<br />

So far we have given simple examples <strong>of</strong> how distributed specialisation can be used to achieve<br />

constant propagation and elimination <strong>of</strong> unnecessary logic primitives. It is worth pointing<br />

out that this operation will be carried out by any reasonable synthesis tool anyway and we are<br />

not claiming that applying constant propagation to circuits is anything new. The strengths<br />

<strong>of</strong> distributed specialisation are its three advantages over low-level hardware optimisation by<br />

synthesis tools.<br />

Firstly, when using components that implement distributed specialisation in a laid out circuit,<br />

the circuit placement can itself be parameterised by the static parameters. This means that<br />

blocks can shrink in size as logic is eliminated and the remainder <strong>of</strong> the circuit components’<br />

positions will be adjusted accordingly. Low-level constant propagation can not achieve this,<br />

even if operating only on a placed rather than placed & routed circuit. While the synthesis<br />

tools will eliminate logic that is not being used, it does not change the positions <strong>of</strong> other<br />

elements <strong>of</strong> the circuit and could not know how to move them anyway since the circuit layout<br />

is only parameterised in the high-level description. By moving specialisation up to the same<br />

level as the layout description (the HDL level) we are able to make sure that the layout is<br />

parameterised and not only propagate constants through a design but also achieve design<br />

compaction.<br />

Compaction has two advantages. It allows specialisation to reduce the overall size <strong>of</strong> the

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