Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 5. SPECIALISATION 111
// Hardware primitive
block and2 (wire a, wire b) ∼ (wire c) attributes { height = 1. width = 1. }{ }
// Specialising when both inputs are known
block and2 (bool a, bool b) ∼ (bool c) attributes { width = 0. height = 0. }
→ c = (a and b).
// Specialising when one input is known
block and2 (bool a, wire b) ∼ (wire c) attributes { width = 0. height = 0. }
→ if a { c = b. } else { c = false. } .
block and2 (wire a, bool b) ∼ (wire c) → (b, a) ; and2 ; c.
Figure 5.2: Distributed specialisation of an and2 block
A B Q
0 0 0
0 1 1
1 0 1
1 1 0
(a) 2-input
B Q
0 1
1 0
(b) A=true
B Q
0 0
1 1
(c) A=false
Figure 5.3: Exclusive-or gate truth tables
A slightly more complicated example is an exclusive-or function. The full and specialised
truth tables for this block are given in Figure 5.3. Here the relationship between B and Q
when A is known is slightly different, if A is false then Q = B however if A is true then Q is
B inverted. Distributed specialisation can describe xor2 blocks which enclose this behaviour,
either connecting the two signals together or generating a simple inverter rather than a full
xor gate. Figure 5.4 shows the Quartz description for xor specialisation.
This example is a particularly significant one because it demonstrates how conditionals in
size expressions can be used to reflect the specialisation in the layout of a circuit. These size
expressions will be propagated through the circuit to create a size expression for the overall
circuit which is dependent on the value of the static parameter.
Specialising the xor2 gate to an inverter does not actually save any logic area on an FPGA,
since logic functions are implemented by look-up tables, however if realised on an ASIC the
difference between 8 transistors to implement an xor function and 2 to implement an inverter
is definitely worth having.