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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 5. SPECIALISATION 110<br />

A B Q<br />

0 0 0<br />

0 1 0<br />

1 0 0<br />

1 1 1<br />

(a) 2-input<br />

B Q<br />

0 0<br />

1 1<br />

(b) A=true<br />

B Q<br />

0 0<br />

1 0<br />

(c) A=false<br />

Figure 5.1: AND gate truth tables<br />

about them, we instead totally replace them <strong>with</strong> Quartz variables.<br />

5.2.1 Specialising Primitives<br />

We will first introduce this simple but powerful idea <strong>with</strong> a basic example: a 2-input logical<br />

and gate. The truth table for a 2-input and gate is shown in Figure 5.1(a), showing that<br />

the output signal Q is only asserted if both the inputs A and B are true. If one <strong>of</strong> the<br />

input signals is known then this truth table can be simplified as shown in Figure 5.1(b) and<br />

Figure 5.1(c). If A is false, then Q always equals false, regardless <strong>of</strong> the value <strong>of</strong> B, while if<br />

A is true then Q takes the value <strong>of</strong> B.<br />

This allows us to describe the specialisation <strong>of</strong> an and gate when the A input is fixed - if it<br />

is fixed <strong>with</strong> value true then the gate should specialise to a wire linking Q and B, while if it<br />

fixed <strong>with</strong> value false then Q should just be statically assigned the value false.<br />

In distributed specialisation we enclose this behaviour <strong>with</strong>in a composite and2 block which<br />

will transparently carry out this operation when connected to a static value. We can use<br />

the Quartz overloading mechanism to select between different possible uses <strong>of</strong> the and gate<br />

primitive - <strong>with</strong> two wire values, or one wire and one known value or two known values - using<br />

the type system, assuming that static values are represented as Quartz booleans. Figure 5.2<br />

illustrates the overloaded Quartz blocks that can describe this operation.<br />

If the two input values are unknown (i.e. they are real dynamic values carried on hardware<br />

wires) then the hardware primitive and2 is selected which elaborates to a primitive gate <strong>with</strong><br />

size 1 × 1. If both inputs are known then no hardware is generated at all and instead a<br />

boolean output variable is generated <strong>with</strong> the value <strong>of</strong> the and operation. If one input is<br />

known then either a wire or a static assignment <strong>of</strong> c to ground is generated.

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