Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 5. SPECIALISATION 109
operated at a low level on a placed and routed circuit and replaced unnecessary functional
components with wires. However, this process leaves the bounding box of the circuit un-
changed and is thus not effective at freeing logic area on the device. In addition this bounding
box can contain long wire lengths which will have a performance impact on the specialised
design, reducing its maximum clock frequency.
An alternative approach to specialising the low level hardware is to generate a specialised
design at a higher level. This however requires that the full process of synthesising, mapping,
placing and routing a design is completed for the specialised circuit - something that will
probably take far too long. This time can be reduced by taking the middle road and gener-
ating a mapped, placed circuit which only then needs to be routed. Design methodologies
which allow fast generation of FPGA bitstreams from this kind of description have been
described [78].
In this chapter we demonstrate how our Quartz placement infrastructure can be used to
specialise designs and illustrate the principle of distributed specialisation.
5.2 Distributed Specialisation
We use the term “distributed specialisation” to describe Quartz blocks which appear to be
hardware elements but which actually contain code which controls their elaboration to pro-
duce simpler hardware if possible. These self-specialising blocks can be seamlessly integrated
into a design to achieve HDL-level support for specialisation.
Distributed specialisation is characterised by the lack of any centralised control, making
specialisation available transparently to the designer. We will also demonstrate the slightly
counter-intuitive concept that distributing the specialisation code into multiple locations
actually makes design verification easier as compared to when specialisation is explicitly
controlled by a “specialise” input, such as has been demonstrated with the Pebble layout
system [49].
Our self-specialising blocks are “clever components” [75], although they are quite different to
those previously demonstrated. Rather than pairing hardware wires with extra information