Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 5. SPECIALISATION 108
is carried out either by the designer or automatically by synthesis tools. The process can
encompass a range of low level logic optimisations such as constant propagation and dead
logic removal (eliminating logic that computes a result which is never used). However, the
increasing role of FPGAs and their potential for run-time reconfiguration raises the possibility
of dynamic specialisation - changing the circuit at run-time.
At present the most common use of run-time reconfiguration is to swap different pre-synthesised
library circuits on and off a chip. However, dynamic specialisation can be used to reconfigure
an FPGA to carry out the same operation but to perform it in some way that is better - for
example using fewer logic resources or being able to run at a higher clock frequency.
Dynamic specialisation becomes a useful option for circuits which do not have static inputs
but do have one or more inputs that changes at a much lower rate than the others. A good
example is a cryptographic processor which may have two inputs: an encryption key and
plaintext data to encrypt. If the key changes much less frequently than the plaintext then
the decryption circuit can usefully be specialised for that key value, producing a design that
is more efficient.
The usefulness of dynamic specialisation depends on the trade-off between the expected
benefit to be gained from specialisation and the time taken to generate a specialised design
and reconfigure the FPGA. This trade-off is not necessarily one purely of time, since it could
be that the desire is to free logic area on the FPGA for other uses rather than purely making
the design run faster.
Dynamic specialisation poses a particular difficulty from the point of view of design verifi-
cation. Standard verification methodologies based on simulation (or even model checking of
the finished design) are not going to be any use for verifying the correctness of designs which
are being produced in the order of seconds rather than days, weeks or months - and very
probably without any human intervention. This suggests that it is appropriate to employ
formal verification and theorem proving for dynamic specialisation to verify the equivalence
of a specialised version to the general-purpose design.
Some success has been reported with this approach in verifying a procedure to partially
evaluate a multiplier circuit using higher-order logic [80]. This partial evaluation procedure