Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 106 erating proof scripts which will automatically prove these theorems using Isabelle’s simplifier and classical reasoner. We have demonstrated our system on a range of combinators including the full prelude and index operators libraries. Large theorems have been proven relatively easily and we have also demonstrated that our system can reveal the flaws in circuit layouts in a useful manner for aiding development, rather than purely giving a false result. Chapter 6 contains some examples of the usage of the layout generation and verification system on a range of complete designs.
Chapter 5 Specialisation In this chapter we illustrate how Quartz can be used to create specialised, placed designs when some input values are known at compile-time. Section 5.1 introduces the benefits of design specialisation and some of its applications. In Section 5.2 we illustrate how we can achieve distributed specialisation transparently using Quartz “clever components” as primitive ele- ments. In Section 5.3 we discuss the limitations of our current infrastructure for distributed specialisation and outline the requirements for an optimal system, while Section 5.4 discusses the role of specialisation code at a higher-level than primitive components. Section 5.5 illus- trates high level specialisation of a multiplier circuit and evaluates the performance impact of compacting designs when logic is optimised away. Section 5.6 summarises this chapter. 5.1 Introduction Design specialisation is a useful tool that can be used to optimise the performance of digital circuits when the values of some inputs are known. It is something that is so commonly used in circuit design as to almost not be worth mentioning with simple optimisations such as replacing a full multiplier by a constant co-efficient multiplier when one input is fixed or, at a meta-level, the choice of selecting a multiplier implementation rather than a full ALU for a circuit that will only perform multiplication. Typically most design specialisation is static specialisation - a design-time optimisation that 107
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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CHAPTER 6. LAYOUT CASE STUDIES 157
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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BIBLIOGRAPHY 179 [41] Y. Li and M.
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BIBLIOGRAPHY 181 [60] L. C. Paulson
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BIBLIOGRAPHY 183 [83] J. Voeten. On
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APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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Appendix B Theoretical Basis for La
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APPENDIX B. THEORETICAL BASIS FOR L
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Appendix C Placed Combinator Librar
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APPENDIX C. PLACED COMBINATOR LIBRA
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APPENDIX D. CIRCUIT LAYOUT CASE STU
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