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Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 105<br />

Once again, an alternative to this would perhaps be to attempt a deep embedding <strong>of</strong> Quartz<br />

in Isabelle and to prove the correctness <strong>of</strong> layouts in terms <strong>of</strong> the compilation function. A<br />

deep embedding, particularly one which encompassed a full compilation procedure, would be<br />

an even more substantial undertaking than this shallow embedding. <strong>Layout</strong> verification based<br />

on a deep embedding <strong>of</strong> compilation (for intersection pro<strong>of</strong>s) and the size inference algorithm<br />

(for validity and containment pro<strong>of</strong>s) would, for each individual design, probably require the<br />

pro<strong>of</strong> <strong>of</strong> significantly fewer theorems but each theorem is likely to be more complex. The<br />

benefit would be an increased level <strong>of</strong> formal assurance in the result but quite how much <strong>of</strong><br />

a benefit this is remains an open question.<br />

Another aspect <strong>of</strong> our system that could be changed is the use <strong>of</strong> containment pro<strong>of</strong>s. We<br />

have based layout verification around the assumption that each block can be contained <strong>with</strong>in<br />

a rectangle and this rectangle can then be used as an abstraction for the block layout in later<br />

pro<strong>of</strong>s. However, for irregular shaped blocks this may not be optimal - for example consider<br />

the case <strong>of</strong> two triangular circuits, which could be laid out inter-locking to form a rectangle<br />

- but only if their size functions are not rectangular. Introducing block boundaries described<br />

by arbitrary functions would massively complicate reasoning and the approach we would<br />

advocate using our system is to describe shapes such as these as new combinators as and<br />

when they are required - these layouts can then be proved as normal. An alternative is to<br />

relax the requirement on containment pro<strong>of</strong>s and verify the containment <strong>of</strong> a set <strong>of</strong> blocks.<br />

This means verifying the layout at a level <strong>of</strong> a set <strong>of</strong> blocks rather than each individual block<br />

in the set.<br />

4.9 Summary<br />

In this chapter we have described a system for verifying Quartz circuit layouts in a shallow<br />

embedding <strong>of</strong> Quartz in Higher-Order Logic using the generic theorem prover Isabelle. We<br />

give Quartz a formal semantics in HOL.<br />

We have described new features <strong>of</strong> the Quartz compiler which support automatic conversion<br />

<strong>of</strong> Quartz descriptions into Isabelle/HOL definitions and the automatic generation <strong>of</strong> pro<strong>of</strong><br />

obligations to verify their layouts. Our modified compiler is also reasonably effective at gen-

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