Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 104 all r ∈ R, heightr and widthr are valid, the height and width expressions inferred for block A will be valid. Proof By induction on the structure of statements and using Theorems 9, 11, 13 and 17. Similar proofs must be completed for the size function for block compositions SI but these are similar and easy. However, if these theorems are simply omitted from the Isabelle theories this makes it im- possible for them to be referred to in proofs for blocks which have manually specified size functions. Manually specified size functions are far from useless - they can be simpler than inferred ones and allow blocks to be allocated sizes that are larger than required. This latter point is particularly important for run-time reconfigurable designs where it may be desirable to allocate the same (maximum) amount of space to a design regardless of how big it actually is and allow all different generated designs to grow or shrink within that boundary. A way around this is to describe the size inference function itself in Isabelle and prove these properties about it using a deep embedding of Quartz. A meta-theorem could then be proved in Isabelle/HOL to provide validity proofs for all size expressions produced by the inference algorithm. Issue 2 appears to mainly be one of implementation. Isabelle’s automated proof tools do produce very good results when their rule sets are correctly configured and further investi- gation is necessary to reveal whether these issues are caused by niceties in the phrasing of theorems or subtle bugs in the way they are applied by the classical reasoner. It should be stressed that where manual intervention in proofs has been necessary it has not required any theorems or lemmas that are not already present in the QuartzLayout library and thus for an experienced user the task is generally an easy one. The third issue is perhaps one of choice. Formal verification is time consuming and difficult. As such it makes sense to apply it only to the parts of a design or design process where it is most likely to yield results. No hardware development system is available that is formally verified from “top to bottom” and in our system we have chosen to implement formal verification for a particular subset, based on particular definitions that we can reason are correct in a semi-formal way.
CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 105 Once again, an alternative to this would perhaps be to attempt a deep embedding of Quartz in Isabelle and to prove the correctness of layouts in terms of the compilation function. A deep embedding, particularly one which encompassed a full compilation procedure, would be an even more substantial undertaking than this shallow embedding. Layout verification based on a deep embedding of compilation (for intersection proofs) and the size inference algorithm (for validity and containment proofs) would, for each individual design, probably require the proof of significantly fewer theorems but each theorem is likely to be more complex. The benefit would be an increased level of formal assurance in the result but quite how much of a benefit this is remains an open question. Another aspect of our system that could be changed is the use of containment proofs. We have based layout verification around the assumption that each block can be contained within a rectangle and this rectangle can then be used as an abstraction for the block layout in later proofs. However, for irregular shaped blocks this may not be optimal - for example consider the case of two triangular circuits, which could be laid out inter-locking to form a rectangle - but only if their size functions are not rectangular. Introducing block boundaries described by arbitrary functions would massively complicate reasoning and the approach we would advocate using our system is to describe shapes such as these as new combinators as and when they are required - these layouts can then be proved as normal. An alternative is to relax the requirement on containment proofs and verify the containment of a set of blocks. This means verifying the layout at a level of a set of blocks rather than each individual block in the set. 4.9 Summary In this chapter we have described a system for verifying Quartz circuit layouts in a shallow embedding of Quartz in Higher-Order Logic using the generic theorem prover Isabelle. We give Quartz a formal semantics in HOL. We have described new features of the Quartz compiler which support automatic conversion of Quartz descriptions into Isabelle/HOL definitions and the automatic generation of proof obligations to verify their layouts. Our modified compiler is also reasonably effective at gen-
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Imperial College of Science, Techno
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Acknowledgements Firstly, I’d lik
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TABLE OF CONTENTS iv 2.5 Isabelle:
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TABLE OF CONTENTS vi 5.3.1 Speciali
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TABLE OF CONTENTS viii C.1.1 fst .
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Chapter 1 Introduction This thesis
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CHAPTER 1. INTRODUCTION 3 B A C Fig
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CHAPTER 1. INTRODUCTION 5 pler, all
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CHAPTER 2. BACKGROUND AND RELATED W
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CHAPTER 3. GENERATING PARAMETERISED
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CHAPTER 6. LAYOUT CASE STUDIES 155
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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BIBLIOGRAPHY 179 [41] Y. Li and M.
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BIBLIOGRAPHY 181 [60] L. C. Paulson
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BIBLIOGRAPHY 183 [83] J. Voeten. On
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APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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Appendix B Theoretical Basis for La
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APPENDIX B. THEORETICAL BASIS FOR L
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Appendix C Placed Combinator Librar
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APPENDIX C. PLACED COMBINATOR LIBRA
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APPENDIX D. CIRCUIT LAYOUT CASE STU
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