Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 102
B
C
A
D
Figure 4.20: The surround combinator
Appendix C.4 gives the Quartz description and correctness proof for this combinator’s layout.
Validity of height and width expressions are proved by auto configured to expand let defin-
itions and using Theorem 11 (z aleq bc). Containment proofs can also most be completed
purely by auto however one requires the use of a variant of Theorem 9.
The true value of the verification methodology comes into play with the intersection proofs.
Once again, these are proved entirely automatically using purely auto - however the error that
was discovered in the layout was discovered because an intersection theorem was not proved.
The error was that C was naively placed with its y co-ordinate defined by heightA+heightD
however this did not take into account of the fact that it was possible for it to overlap block E
under some circumstances. A simple correction to define the y co-ordinate as the maximum
of the height of E or A and D was sufficient to produce a valid layout.
This is still a relatively simple layout for this combinator. A more complex layout description
could use conditionals to compare the heights and widths of the various blocks and adjust
their relative placement accordingly (for example, the B and E blocks could be aligned with
the bottom of the combinator as a whole rather than the bottom of the A block if they have
a greater height than A).
E