Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 100
R
R R R
R
R
R R
R
R
R R R
R
R
R
R
R
R
R R R
R
R
R
R R R
Figure 4.18: An H-Tree arrangement of R blocks for n = 5
block htree (int n, block R (‘a, ‘a) ∼ ‘a) (‘a i [m]) ∼ (‘a o) {
const m = 2 ∗∗ n.
‘a st1 in[m/2], st2 in[m/2], st1 out, st2 out.
if n == 0 { o = i[0]. } else {
i ; half (m/2) ; (st1 in, st2 in) at (0,0).
if (n mod 2 == 0) {
// Vertical sub−tree arrangement
st1 in ; htree (n−1, R) ; st1 out at (0,0).
(st1 out, st2 out) ; R ; o
at (0, height(st1 in ; htree (n−1, R) ; st1 out)).
st2 in ; htree (n−1, R) ; st2 out
at (0, height(st1 in;htree (n−1, R);st1 out) +
height ((st1 out, st2 out);R;o)).
} else {
// Horizontal sub−tree arrangement
st1 in ; htree (n−1, R) ; st1 out at (0,0).
(st1 out, st2 out) ; R ; o
at (width(st1 in ;htree (n−1, R) ; st1 out), 0).
st2 in ; htree (n−1, R) ; st2 out
at (width(st1 in;htree (n−1, R);st1 out) +
width ((st1 out, st2 out);R;o), 0).
} .
} .
}
Figure 4.19: Quartz description for the a H-tree combinator
R
R
R