Verification of Parameterised FPGA Circuit Descriptions with Layout ...

Chapter 1
Introduction
This thesis presents a framework for the design and verification of parameterised hardware
libraries with layout information. Our framework is based around the Quartz hardware
description language, which supports higher-order combinators and relational operators de-
signed to promote concise descriptions and formal verification of design function. We extend
the Quartz language and compiler framework to allow the circuit designer to add layout
information and formally verify the correctness of parameterised layouts rather than relying
on automatic placement.
The framework includes a conservative extension to the class of Quartz expressions to provide
the extra functionality which we show is required to describe generic layouts for both recur-
sively and iteratively described circuits, a compiler infrastructure for compiling designs with
layout information into parameterised hardware libraries and a proof tool with a library of
theorems to automate the verification of circuit layouts. The use of the framework is demon-
strated on a range of example designs including median filter and matrix multiplier circuits
and we show that including layout information in designs can improve their performance by
up to 82%, reduce logic area by 40-60% and reduce power consumption in comparison with
using the standard Xilinx place and route tools.
The potential of this framework to support dynamic specialisation applications is also il-
lustrated and we introduce the concept of distributed specialisation to achieve HDL-level
specialisation of circuits in a manner such that the specialised circuits can easily be verified.
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