Verification of Parameterised FPGA Circuit Descriptions with Layout ...

CHAPTER 4. VERIFYING CIRCUIT LAYOUTS 99
block irregular grid (block A ‘a1 ∼ ‘a2, block B ‘b1 ∼ ‘b2,
block C ‘c1 ∼ ‘c2, block D ‘d1 ∼ ‘d2, block E ‘e1 ∼ ‘e2)
(‘a1 a1, ‘b1 b1, ‘c1 c1, ‘d1 d1, ‘e1 e1) ∼
(‘a2 a2, ‘b2 b2, ‘c2 c2, ‘d2 d2, ‘e2 e2)
attributes {
height = max (height (a1;A;a2) + height(b1;B;b2),
height(a1;A;a2)+height(c1;C;c2)+height(d1;D;d2),
height(e1;E;e2)+height(d1;D;d2)).
width = max (width(a1;A;a2) + width(e1;E;e2),
width(b1;B;b2) + width(c1;C;c2) + width(e1;E;e2),
width(b1;B;b2) + width(d1;D;d2)).
} {
a1 ; A ; a2 at (0,0).
b1 ; B ; b2 at (0, height(a1 ; A ; a2)).
c1 ; C ; c2 at (width(b1 ;B ; b2), height(a1 ; A ; a2)).
d1 ; D ; d2
at (width (b1 ;B ; b2),
max (height (c1 ;C ; c2) + height(a1 ;A ; a2), height(e1 ; E ; e2))).
e1 ; E ; e2
at (max (width (a1 ;A ;a2), width(c1 ;C ; c2) + width(b1 ;B ; b2)), 0).
}
Figure 4.17: Quartz description for the irregular grid arrangement shown in Figure 4.16
script execution times for the two combinators, with the inferred size combinator requiring
2 min 37s to execute while the manually specified size combinator required only 31s. In
both cases proof scripts required some minor amendments from the auto-generated defaults,
although these were relatively simple.
The most important observation from this combinator stems from proof of its four intersection
theorems. During proofs of these theorems a bug in the layout description was discovered,
illustrating that the proof process can have a role in the early debugging of this kind of layout
description. While one downside of theorem proving as opposed to model checking is that it
does not provide counter-examples, failure to prove an intersection proof obligation tends to
leave a proof state that with only a little massaging clearly reveals the source of the error.
Appendix C.3 gives the full proof script for this combinator.
4.7.3 H-Tree
A H-tree is type of layout shown in Figure 4.18. It is of particular interest in circuit design
since it can be used to lay out a tree-shaped circuit in a square block with balanced wire