Verification of Parameterised FPGA Circuit Descriptions with Layout ...

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TABLE OF CONTENTS ix D.1.11 Theory nextstate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 D.1.12 Theory filter core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 D.1.13 Theory filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 D.2 Butterfly Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 D.2.1 Quartz description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 D.2.2 Theory comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 D.2.3 Theory sort2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 D.2.4 Theory butterfly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 D.2.5 Theory merger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 D.3 Matrix Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 D.3.1 Quartz Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 D.3.2 Theory cube cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 D.3.3 Theory cube . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 D.3.4 Theory matmultcell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 D.3.5 Theory matmult . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Chapter 1 Introduction This thesis presents a framework for the design and verification of parameterised hardware libraries with layout information. Our framework is based around the Quartz hardware description language, which supports higher-order combinators and relational operators de- signed to promote concise descriptions and formal verification of design function. We extend the Quartz language and compiler framework to allow the circuit designer to add layout information and formally verify the correctness of parameterised layouts rather than relying on automatic placement. The framework includes a conservative extension to the class of Quartz expressions to provide the extra functionality which we show is required to describe generic layouts for both recur- sively and iteratively described circuits, a compiler infrastructure for compiling designs with layout information into parameterised hardware libraries and a proof tool with a library of theorems to automate the verification of circuit layouts. The use of the framework is demon- strated on a range of example designs including median filter and matrix multiplier circuits and we show that including layout information in designs can improve their performance by up to 82%, reduce logic area by 40-60% and reduce power consumption in comparison with using the standard Xilinx place and route tools. The potential of this framework to support dynamic specialisation applications is also il- lustrated and we introduce the concept of distributed specialisation to achieve HDL-level specialisation of circuits in a manner such that the specialised circuits can easily be verified. 1
Page 1 and 2: Imperial College of Science, Techno
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CHAPTER 3. GENERATING PARAMETERISED
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Chapter 4 Verifying Circuit Layouts
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CHAPTER 4. VERIFYING CIRCUIT LAYOUT
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CHAPTER 6. LAYOUT CASE STUDIES 131
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CHAPTER 7. CONCLUSION AND FUTURE WO
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Bibliography [1] A. Aggoun and N. B
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BIBLIOGRAPHY 177 [19] H. Gelernter.
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BIBLIOGRAPHY 179 [41] Y. Li and M.
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BIBLIOGRAPHY 181 [60] L. C. Paulson
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BIBLIOGRAPHY 183 [83] J. Voeten. On
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APPENDIX A. QUARTZ LANGUAGE GRAMMAR
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Appendix B Theoretical Basis for La
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APPENDIX B. THEORETICAL BASIS FOR L
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Appendix C Placed Combinator Librar
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APPENDIX C. PLACED COMBINATOR LIBRA
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