Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.

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Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D. [R11] M. Alioto, G. Palumbo, "Analysis and Comparison on Full Adder Block in Sub-Micron Technology,” IEEE Trans. on VLSI Systems, vol. 10, no. 6, pp. 806-823, Dec. 2002. [R12] M. Alioto, G. Palumbo, "A Simple Strategy for Optimized Design of One-Level Carry-Skip Adders,” IEEE Trans. on CAS part I, vol. 50, no. 1, pp. 141-148, Jan. 2003. [R13] M. Alioto, G. Palumbo, "Design Strategies for Source Coupled Logic Gates,” IEEE Trans. on CAS part I, vol. 50, no. 5, pp. 640-654, May 2003. [R14] M. Alioto, R. Mita, G. Palumbo, "Performance Evaluation of the Low-Voltage CML D-Latch Topology,” Integration - The VLSI Journal, Special Issue in Analog and Mixed-Signal IC Design and Design Methodologies (edited by Francisco V. Fernandez), vol. 36, no. 4, pp. 191-209, Nov. 2003. [R15] M. Alioto, G. Palumbo, M. Poli, "Evaluation of Energy Consumption in RC Ladder Circuits Driven by a Ramp Input,” IEEE Trans. on VLSI Systems, vol. 12, no. 10, pp. 1094-1107, Oct. 2004. [R16] M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Modeling and Evaluation of Positive-Feedback Source-Coupled Logic", IEEE Trans. on CAS – part I, vol. 51, no. 12, pp. 2345-2355, Dec. 2004. [R17] M. Alioto, S. Bernardi, A. Fort, S. Rocchi, V. Vignoli, "An Efficient Implementation of PRNGs Based on the Digital Sawtooth Map", International Journal of Circuit Theory and Applications, vol. 32, no. 6, pp. 615-627, Nov./Dec. 2004. [R18] M. Alioto, G. Palumbo, "Power-Delay Optimization of D-Latch/MUX Source Coupled Logic Gates," International Journal of Circuit Theory and Applications, vol. 33, no. 1, pp. 65-86, Jan./Feb. 2005. [R19] M. Alioto, G. Palumbo, "Design strategies of Cascaded CML Gates," IEEE Transactions on CAS – part II, vol. 53, no. 2, pp. 85-89, Feb. 2006. [R20] M. Alioto, G. Palumbo, "Modeling and Design Considerations on CML Gates under High-Current Effects," International Journal of Circuit Theory and Applications, vol. 33, no. 6, pp. 503-518, Nov./Dec. 2005. [R21] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "A Feedback Strategy to Improve the Entropy of a Chaos-Based Random Bit Generator," IEEE Transactions on CAS – Part I, vol. 53, no. 2, pp. 326-337, Feb. 2006. 6
Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D. [R22] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Low Hardware Complexity PRBGs Based on a Piecewise-Linear Chaotic Map," IEEE Transactions on CAS – Part II, vol. 53, no. 5, pp. 329- 333, May 2006. [R23] M. Alioto, A. D. Grasso, G. Palumbo, "Design of Cascaded ECL Gates with a Power Constraint", IEE Electronics Letters, vol. 42, no. 4, pp. 211- 212, 16 th February 2006. [R24] M. Alioto, G. Palumbo, M. Poli, "Energy Consumption in RC Tree Circuits", IEEE Trans. on VLSI Systems, vol. 14, no. 5, pp. 452-461, May 2006. [R25] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "The Digital Tent Map: Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits," IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 5, pp. 1451-1458, Oct. 2006. [R26] M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Exploiting Hysteresys in MCML Circuits", IEEE Trans. on Circuits and Systems - part II, vol. 53, no. 11, pp. 1170-1174, Nov. 2006. [R27] M. Alioto, R. Mita, G. Palumbo, "Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers", IEEE Trans. on Circuits and Systems - part II, vol. 53, no. 11, pp. 1165-1169, Nov. 2006. [R28] M. Alioto, G. Palumbo, "Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework," IEEE Circuits and Systems Magazine, vol. 6, no. 4, pp. 40-59, 2006. [R29] M. Alioto, G. Palumbo, "Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison," in print on IEEE Trans. on VLSI Systems. [R30] M. Alioto, G. Di Cataldo, G. Palumbo, "Mixed Full Adder Topologies for High-Performance Low- Power Arithmetic Circuits," in print on Microelectronics Journal. [R31] T. Addabbo, M. Alioto, A. Fort, A. Pasini, S.Rocchi, V. Vignoli, "A Class of Maximum-Period Nonlinear Congruential Generators Derived From The Sawtooth Chaotic Map", accepted to IEEE Trans. on Circuits and Systems - part I. [R32] M. Alioto, G. Palumbo, "Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers," accepted to IEEE Trans. on Circuits and Systems – part II. 7
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