Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.

Curriculum vitae of
prof. Massimo Bruno Cristiano Alioto,
Ph.D.

Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.
General information
Massimo Bruno Cristiano Alioto was born in Brescia (Italy) in 1972, and currently lives
in Siena (Italy).
In 2005 he is appointed Associate Professor in Italy, and is officially engaged in 2006
by the Faculty of Engineering of the University of Siena.
Since 2002 he has been teaching undergraduate, graduate and post-graduate courses on
Electronics at the Faculty of Engineering of Siena.
In 2002 he joins the Faculty of Engineering of the University of Siena as a Research
Associate, and a few months later he becomes Assistant Professor of Electronics in the
same faculty.
In 2001 he takes the Ph.D. degree in Electrical Engineering at the Engineering Faculty of
Catania (Italy). In the same year he teaches the undergraduate course on Microelectronics in
the same faculty.
In 1998 he starts the Ph.D. in Electrical Engineering.
In 1997 he takes the Laurea degree on Electronics Engineering at the Engineering
Faculty of Catania (Italy), and achieved the license as a professional engineer.
Teaching activity
In 2005 and 2006 he is lecturer of the short course Timing and Adders Optimization at
the Electronic Engineering Faculty of Udine (Italy), and in 2006 of the short course Areapower-delay
trade-offs in VLSI circuits at the Electronic Engineering Faculty of Catania
(Italy).
Since 2004 he teaches the graduate course Electronics and Digital Systems Technology,
which is focused on advanced aspects on the VLSI design (clock network, clock skew, low
power design, metrics for circuit optimization, physical design, cell library design, areapower-time
trade-off, arithmetic circuits).
Since 2003 he teaches a module of 30 hours for the undergraduate course Digital
Systems Electronics at he Engineering Faculty of Siena, dealing with the design of FPGAs
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Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.
through HDL description and standard design flows. Since 2002 he teaches the
undergraduate course Electronics, which introduces the basics of analog circuits.
In 2002, he teaches the post-graduate course on Hardware Architectures of Digital
Systems for the post-graduate master Sicurnet, organized by the University of Siena with
many other partners, and a module of the course Electronics II and courses Electronics I and
Laboratory of Electronic Circuits Design. Only in 2002 he also teaches the graduate short
courses Electronics II, Electronics I and Laboratory of Electronic Circuit Design at the
Engineering faculty of Siena. In the same year he is the author of the on-line course Ipertext
Guide to Analog/Digital Circuits through the SPICE simulator.
In 2001 he teaches the undergraduate course on Microelectronics in the Engineering
Faculty of Catania.
From 1997 to 2001 he gave several lectures on graduate courses on analog and digital
electronics at the Faculty of Electronics Engineering of Catania.
Since 1997 he has been supervising several M.Sc. and B.Sc. thesis focused on aspects
related to the modeling and the design of digital circuits, at the transistor, gate and system
level.
Scientific activity
The scientific activity of Dr. Alioto is focused on electronic integrated circuits with
emphasis on the digital circuits with a high performance, in terms of high speed and/or low
power consumption. In particular, his main research interests and publications can be
classified into
• modeling and design of (bipolar) emitter-coupled and (CMOS) source-coupled
logic circuits (ECL, CML, MCML)
• low-power and adiabatic circuits
• optimized design of logic and arithmetic circuits (adders at the transistor and gate
level, high-fanin multiplexers)
• circuits for cryptography (true- and pseudo- random number generators, circuits
resistance to Differential Power Analysis attacks)
• design for variability in nanometer technologies
He is co-author of the book Model and Design of Bipolar and MOS Current-Mode Logic
(CML, ECL and SCL Digital Circuits) published by Springer in 2005. He is author or co-
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Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.
author of 31 papers on international journals, 45 papers on international conferences and 3
papers on national journals (see the detailed list of publication after this section).
Since 2000, he has been a reviewer of several papers for the following international
journals
• IEEE Transactions on Circuits and Systems – Part I
• IEEE Transactions on Circuits and Systems – Part II
• Microelectronics Journal
• Journal of Low Power Electronics
• IEE Electronics Letters
• IEE Proceedings on Circuits, Devices & Systems
• IEE Proceedings on Computers and Digital Techniques
• Journal of Embedded Computing
• Integration – The VLSI journal
and for the international conferences ISCAS2005, ECCTD2005, ISCAS2004, ICECS2003,
ISCAS2003, ISCAS2002, IECON2001.
In 2005 he is member of the Technical Committee of the conference PATMOS2005 for
the area “Circuits, low-power”. In 2004 he was Chairman of the parallel sessions
“Clocking” and “Flip-Flops” at the ISCAS conference. Since 2006 he is member of the
VLSI Systems and Applications Technical Committee of the IEEE Circuits and Systems
Society, and since 2005 he is member of the Technical Program Committee of the
PATMOS international workshop.
He has presented various papers at international conferences (with referral to the list of
publications, the papers [C31], [C30], [C29], [C24], [C23], [C22], [C21], [C20], [C14],
[C8], [C5], [C4]).
He participated in national research projects, such as PAR2003 for the “Study of
Differential Power Analysis-immune cryptographic algorithms and devices”, and FIRB on
the “Reconfigurable platform for wide-band mobile communications” from 2001 to 2003, in
collaboration with Marconi Mobile. In 2006, he leads the Unit of Siena in the context of the
project PRIN2006 “Conventional (bulk) versus emerging nanoscale CMOS technologies: a
comparative evaluation from the device to the system level”.
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Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.
List of publications of prof. Massimo Bruno Cristiano Alioto
Books
[B1] M. Alioto, G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL
and SCL Digital Circuits), Springer, 2005.
International journals
[R1] M. Alioto, G. Palumbo, "Highly Accurate and Simple Models for CML and ECL gates", IEEE
Trans. on CAD, vol. 18, no. 9, pp. 1369-1375, September 1999.
[R2] M. Alioto, G. Palumbo, "CML and ECL: Optimized Design and Comparison," IEEE Trans. on CAS
part I, vol. 46, no. 11, pp. 1330-1341, November 1999.
[R3] M. Alioto, G. Palumbo, "Modeling and Optimized Design of Current Mode MUX/XOR and D Flip-
Flop," IEEE Trans. on CAS part II, Vol. 47, no. 5, pp. 452-461, May 2000.
[R4] M. Alioto, G. Palumbo, "Performance Evaluation of Adiabatic Gates," IEEE Trans. on CAS part I,
vol. 47, no. 9, pp. 1297-1308, September 2000.
[R5] M. Alioto, G. Palumbo, "Oscillation Frequency in CML and ESCL Ring Oscillators,” IEEE Trans.
on CAS part I, vol. 48, no. 2, pp. 210-214, February 2001.
[R6] M. Alioto, G. Palumbo, "Power Estimation in Adiabatic Circuits: A Simple and Accurate Model,"
IEEE Trans. on VLSI Systems, vol. 9, no. 5, pp. 608-615, October 2001.
[R7] M. Alioto, G. Palumbo, S. Pennisi, "Modeling of Source Coupled Logic Gates," International
Journal of Circuit Theory and Applications, vol. 30, no. 4, pp. 459-477, 2002.
[R8] M. Alioto, G. Di Cataldo, G. Palumbo, "Design of Low-Power High-Speed Bipolar Frequency
Dividers," IEE Electronics Letters, vol. 38, no. 4, pp. 158-160, 14 th February 2002.
[R9] M. Alioto, G. Palumbo, "NAND/NOR Adiabatic Gates: Power Consumption Evaluation and
Comparison versus the Fan-In,” IEEE Trans. on CAS part I, vol. 49, no. 9, pp. 1253-1262,
September 2002.
[R10] M. Alioto, G. Palumbo, "Optimized Design of High Fan-In Multiplexers Using Tri-State Buffers,”
IEEE Trans. on CAS part I, vol. 49, no. 10, pp. 1500-1505, Oct. 2002.
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Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.
[R11] M. Alioto, G. Palumbo, "Analysis and Comparison on Full Adder Block in Sub-Micron
Technology,” IEEE Trans. on VLSI Systems, vol. 10, no. 6, pp. 806-823, Dec. 2002.
[R12] M. Alioto, G. Palumbo, "A Simple Strategy for Optimized Design of One-Level Carry-Skip
Adders,” IEEE Trans. on CAS part I, vol. 50, no. 1, pp. 141-148, Jan. 2003.
[R13] M. Alioto, G. Palumbo, "Design Strategies for Source Coupled Logic Gates,” IEEE Trans. on CAS
part I, vol. 50, no. 5, pp. 640-654, May 2003.
[R14] M. Alioto, R. Mita, G. Palumbo, "Performance Evaluation of the Low-Voltage CML D-Latch
Topology,” Integration - The VLSI Journal, Special Issue in Analog and Mixed-Signal IC Design and
Design Methodologies (edited by Francisco V. Fernandez), vol. 36, no. 4, pp. 191-209, Nov. 2003.
[R15] M. Alioto, G. Palumbo, M. Poli, "Evaluation of Energy Consumption in RC Ladder Circuits Driven
by a Ramp Input,” IEEE Trans. on VLSI Systems, vol. 12, no. 10, pp. 1094-1107, Oct. 2004.
[R16] M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Modeling and Evaluation of Positive-Feedback
Source-Coupled Logic", IEEE Trans. on CAS – part I, vol. 51, no. 12, pp. 2345-2355, Dec. 2004.
[R17] M. Alioto, S. Bernardi, A. Fort, S. Rocchi, V. Vignoli, "An Efficient Implementation of PRNGs
Based on the Digital Sawtooth Map", International Journal of Circuit Theory and Applications, vol.
32, no. 6, pp. 615-627, Nov./Dec. 2004.
[R18] M. Alioto, G. Palumbo, "Power-Delay Optimization of D-Latch/MUX Source Coupled Logic
Gates," International Journal of Circuit Theory and Applications, vol. 33, no. 1, pp. 65-86, Jan./Feb.
2005.
[R19] M. Alioto, G. Palumbo, "Design strategies of Cascaded CML Gates," IEEE Transactions on CAS –
part II, vol. 53, no. 2, pp. 85-89, Feb. 2006.
[R20] M. Alioto, G. Palumbo, "Modeling and Design Considerations on CML Gates under High-Current
Effects," International Journal of Circuit Theory and Applications, vol. 33, no. 6, pp. 503-518,
Nov./Dec. 2005.
[R21] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "A Feedback Strategy to Improve the
Entropy of a Chaos-Based Random Bit Generator," IEEE Transactions on CAS – Part I, vol. 53, no.
2, pp. 326-337, Feb. 2006.
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Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.
[R22] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Low Hardware Complexity PRBGs Based
on a Piecewise-Linear Chaotic Map," IEEE Transactions on CAS – Part II, vol. 53, no. 5, pp. 329-
333, May 2006.
[R23] M. Alioto, A. D. Grasso, G. Palumbo, "Design of Cascaded ECL Gates with a Power Constraint",
IEE Electronics Letters, vol. 42, no. 4, pp. 211- 212, 16 th February 2006.
[R24] M. Alioto, G. Palumbo, M. Poli, "Energy Consumption in RC Tree Circuits", IEEE Trans. on VLSI
Systems, vol. 14, no. 5, pp. 452-461, May 2006.
[R25] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "The Digital Tent Map: Performance
Analysis and Optimized Design as a Source of Pseudo-Random Bits," IEEE Transactions on
Instrumentation and Measurement, vol. 55, no. 5, pp. 1451-1458, Oct. 2006.
[R26] M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Exploiting Hysteresys in MCML Circuits", IEEE
Trans. on Circuits and Systems - part II, vol. 53, no. 11, pp. 1170-1174, Nov. 2006.
[R27] M. Alioto, R. Mita, G. Palumbo, "Design of High-Speed Power-Efficient MOS Current-Mode Logic
Frequency Dividers", IEEE Trans. on Circuits and Systems - part II, vol. 53, no. 11, pp. 1165-1169,
Nov. 2006.
[R28] M. Alioto, G. Palumbo, "Power-Aware Design Techniques for Nanometer MOS Current-Mode
Logic Gates: a Design Framework," IEEE Circuits and Systems Magazine, vol. 6, no. 4, pp. 40-59,
2006.
[R29] M. Alioto, G. Palumbo, "Impact of Supply Voltage Variations on Full Adder Delay: Analysis and
Comparison," in print on IEEE Trans. on VLSI Systems.
[R30] M. Alioto, G. Di Cataldo, G. Palumbo, "Mixed Full Adder Topologies for High-Performance Low-
Power Arithmetic Circuits," in print on Microelectronics Journal.
[R31] T. Addabbo, M. Alioto, A. Fort, A. Pasini, S.Rocchi, V. Vignoli, "A Class of Maximum-Period
Nonlinear Congruential Generators Derived From The Sawtooth Chaotic Map", accepted to IEEE
Trans. on Circuits and Systems - part I.
[R32] M. Alioto, G. Palumbo, "Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers,"
accepted to IEEE Trans. on Circuits and Systems – part II.
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Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.
International conferences
[C1] M. Alioto, G. Palumbo, "Novel Simple Models of CML Propagation Delay", IEEE Proc. GLS
VLSI'98, Lafayette, pp. 270-274, February 1998.
[C2] M. Alioto, G. Di Cataldo, G. Palumbo, "General and Simple Model of the Propagation Delay of
Emitter Follower Stage", Proc. of MIXDES'98, Lodz (Poland), pp. 121-124, June 1998.
[C3] M. Alioto, G. Palumbo, "Design of CML Gate with the Best Propagation Delay", Proc. of ICECS'98,
Lisboa (Portugal), pp. 287-290, September 1998.
[C4] M. Alioto, G. Palumbo, "Adiabatic Gates: a Critical Point of View", Proc. of ECCTD'99, Stresa, pp.
129-132, September 1999.
[C5] M. Alioto, G. Palumbo, "Comparison on CMOS Full Adders in Different Design Styles with
Emphasis on Low-Power Topologies", Proc. of ECCTD'99, Stresa, pp. 519-522, September 1999.
[C6] M. Alioto, G. Palumbo, "High-Speed Bipolar MUX Modeling and Design", Proc. of ISCAS2000,
Geneva, pp. V/1-4, May 2000.
[C7] M. Alioto, G. Palumbo, "Evaluation of Power Consumption in Adiabatic Circuits", Proc. of
ISCAS2000, Geneva, pp. II/629-632, May 2000.
[C8] M. Alioto, G. Palumbo, "Modeling of Power Consumption of Adiabatic Gates versus Fan In and
Comparison with Conventional Gates", Proc. of PATMOS2000, Gottingen, pp. 265-275, September
2000.
[C9] M. Alioto, G. Di Cataldo, G. Palumbo, "CML Ring Oscillators: Oscillation Frequency", Proc. of
ISCAS2001, Sydney, pp. IV/112-115, May 2001.
[C10] M. Alioto, G. Palumbo, S. Pennisi, "Predicting Propagation Delay in SCL Gates", Proc. of
ECCTD’01, Espoo (Finland), pp. III/209-212, August 2001.
[C11] M. Alioto, G. Palumbo, "Optimized Design of Carry-Bypass Adders", Proc. of ECCTD’01, Espoo
(Finland), pp. II/245-248, August 2001.
[C12] M. Alioto, G. Palumbo, "Optimized Design of High Fan-in Multiplexers Using Switches with
Driving Capability", Proc. of ICECS’01, Malta, pp. 737-740, September 2001.
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Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.
[C13] M. Alioto, G. Palumbo, S. Pennisi, "Delay Estimation of SCL Gates with Output Buffer", Proc. of
ICECS’01, Malta, pp. 719-722, September 2001.
[C14] M. Alioto, G. Palumbo, "Power-Delay Trade-offs in SCL Gates", Proc. of ISCAS2002, Phoenix
(USA), pp. III/249-252, May 2002.
[C15] M. Alioto, G. Palumbo, M. Poli, "An Approach to Energy Consumption Modeling in RC Ladder
Circuits", Proc. of PATMOS 2002, Sevilla (Spain), pp. 239-246, Sept. 2002.
[C16] M. Alioto, G. Palumbo, "Modeling Propagation Delay of MUX, XOR and D-Latch Source-Coupled
Logic Gates", Proc. of PATMOS 2002, Sevilla (Spain), pp. 429-437, Sept. 2002.
[C17] M. Alioto, G. Di Cataldo, G. Palumbo, "Design Guidelines for Bipolar Frequency Dividers", Proc.
of ICECS 2002, pp. 521-524, Dubrovnik (Croatia), September 2002.
[C18] M. Alioto, R. Mita, G. Palumbo, "Analysis and Comparison of Low-Voltage CML D-Latch", Proc.
of ICECS2002, pp. 737-740, Dubrovnik (Croatia), September 2002.
[C19] M. Alioto, G. Palumbo, "Design of MUX, XOR and D-Latch SCL gates", Proc. of ISCAS2003,
Bangkok (Thailand), pp. V/261-264, May 2003.
[C20] M. Alioto, S. Bernardi, A. Fort, S. Rocchi – V. Vignoli, "On the Suitability of Digital Maps for
Integrated Pseudo-RNGs", Proc. of ECCTD2003, pp. III/349-352, Krakòw (Poland), Sept. 2003.
[C21] M. Alioto, G. Palumbo, "Mixed Logic Styles for High-Speed Low-Power Arithmetic Circuits",
Proc. of ECCTD2003, pp. II/101-104, Krakòw (Poland), Sept. 2003.
[C22] M. Alioto, S. Bernardi, A. Fort, S. Rocchi, V. Vignoli, "Analysis and Design of Digital PRNGs
Based on the Discretized Sawtooth Map", Proc. of ICECS2003, pp. 427-430, Sharjah (United Arab
Emirates), Dec. 2003.
[C23] M. Alioto, G. Palumbo, M. Poli, "A Gate-Level Strategy to Design Carry Select Adders", Proc. of
ISCAS2004, pp. II/465-468, Vancouver (Canada), May 2004.
[C24] M. Alioto, A. Fort, L. Pancioni, S. Rocchi, V. Vignoli, "Positive-Feedback Source-Coupled Logic:
a Delay Model", Proc. of ISCAS2004, pp. II/641-644, Vancouver (Canada), May 2004.
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Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.
[C25] T. Addabbo, M. Alioto, S. Bernardi, A. Fort, S. Rocchi, V. Vignoli, "The Digital Tent Map:
Performance Analysis and Optimized Design as a Source of Pseudo-Random Bits", Proc. of
IMTC2004, pp. 1301-1304, Como (Italy), May 2004.
[C26] M. Alioto, G. Palumbo, M. Poli, "A Simple Model of Energy Consumption for RC Ladder Networks
Driven by an Exponential Input", Proc. of MIXDES2004, pp. 315-319, Szczecin (Poland), June 2004.
[C27] M. Alioto, G. Palumbo, "A Delay Model Of CML Gates Valid under High-Current Effects", Proc. of
MWSCAS2003, pp. 1556- 1559, Cairo (Egypt), Dec. 2003.
[C28] T. Addabbo, M. Alioto, S. Bernardi, A. Fort, S. Rocchi, V. Vignoli, "Hardware-Efficient PRBGs
Based on 1-D Piecewise Linear Chaotic Maps", Proc. of ICECS2004, pp. 242-245, Tel Aviv (Israel),
Dec. 2004.
[C29] M. Alioto, G. Palumbo, "Design Techniques for Low-Power Cascaded CML Gates", Proc. of
ISCAS2005, pp. 4685-4688, Kobe (Japan), May 2005.
[C30] M. Alioto, A. Fort, L. Pancioni, S. Rocchi, V. Vignoli, "An Approach to the Design of PFSCL
Gates", Proc. of ISCAS2005, pp. 2437-2440, Kobe (Japan), May 2005.
[C31] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Long Period Pseudo Random Bit
Generators Derived from a Discretized Chaotic Map", Proc. of ISCAS2005, pp. 892-895, Kobe
(Japan), May 2005.
[C32] M. Alioto, G. Palumbo, M. Poli , "Energy Consumption in RC Tree Circuits with Exponential
Inputs: an Analytical Model", Proc. of PATMOS 2005, pp. 355-363, Leuven (Belgium), Sept. 2005.
[C33] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Uniform-Distributed Noise Generator
Based on a Chaotic Circuit", Proc of IMTC 2006, pp. 1156-1160, Sorrento (Italy), April 2006.
[C34] M. Alioto, G. Palumbo, "Delay Uncertainty Due to Supply Variations in Static and Dynamic Full
Adders", Proc. of ISCAS 2006, pp. 767-770, Kos (Greece), May 2006.
[C35] M. Alioto, G. Palumbo, "Nanometer MCML Gates: Models and Design Considerations", Proc. of
ISCAS 2006, pp. 3862-3865, Kos (Greece), May 2006.
[C36] M. Alioto, L. Pancioni, S. Rocchi, V. Vignoli, "Analysis and Design of MCML Gates with
Hysteresis", Proc. of ISCAS 2006, pp. 1263-1266, Kos (Greece), May 2006.
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Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.
[C37] M. Alioto, G. Palumbo, M. Poli, "Efficient Output Transition Time Modeling in CMOS Gates with
Ramp/Exponential Inputs", Proc. of ISCAS 2006, pp. 5127-5130, Kos (Greece), May 2006.
[C38] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "A Technique to Design High Entropy
Chaos-Based True Random Bit Generators", Proc. of ISCAS 2006, pp. 1183-1186, Kos (Greece), May
2006.
[C39] M. Alioto, A. D. Grasso, G. Palumbo, "Design of Cascaded ECL Gates with a Power Constraint",
Proc. of PRIME 2006, pp. 233-236, Otranto (Italy), June 2006.
[C40] M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Power Modeling of Precharged Address Bus and
Application to Multi-bit DPA Attacks to DES Algorithm", Proc. of PATMOS 2006, pp. 593-602,
Montpellier (France), Sept. 2006.
[C41] M. Alioto, M. Poli, S. Rocchi, V. Vignoli, "Techniques to Enhance the Resistance of Precharged
Busses to Differential Power Analysis", Proc. of PATMOS 2006, pp. 624-633, Montpellier (France),
Sept. 2006.
[C42*] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Entropy Enhancement in a Chaos-Based
True Random Bit Generators", Proc. of NOLTA 2006, pp. 372-378, Bologna (Italy), Sept. 2006.
[C43*] M. Alioto, R. Mita, G. Palumbo, "A Design Methodology for High-Speed Low-Power MCML
Frequency Dividers", Proc. of ICECS2006, pp. 1308-1311, Nice (France), Dec. 2006.
[C44*] M. Alioto, G. Palumbo, "Modeling of Delay Variability due to Supply Variations in Pass-Transistor
and Static Full Adders", Proc. of ICECS2006, pp. 518-521, Nice (France), Dec. 2006.
[C45*] T. Addabbo, M. Alioto, A. Fort, S. Rocchi, V. Vignoli, "Efficient Post-Processing Module for a
Chaos-based Random Bit Generator ", accepted to ICECS2006, Nice (France), Dec. 2006.
[C46*] T. Addabbo, M. Alioto, A. Fort, M. Mugnaini, S. Rocchi, V. Vignoli, "Implementation-Efficient
Maximum-Period Nonlinear Congruential Generators", accepted to IMTC 2007, Warsaw (Poland),
May. 2007.
National journals
[I1] M. Alioto, G. Palumbo, C. Strano, "Circuiti adiabatici: per minimizzare la dissipazione di potenza",
Automazione e Strumentazione - Elettronica Industriale, No. 3, pag. 49-54, marzo 1998.
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Curriculum vitae of prof. Massimo Bruno Cristiano Alioto, Ph.D.
[I2] M. Alioto, G. Palumbo, "Famiglie logiche bipolari ECL E CML", Automazione e Strumentazione -
Elettronica Industriale, No. 9, pag. 49-56, ottobre 1998.
[I3] M. Alioto, R. Mita, G. Palumbo, "Memorie ferroelettriche", Automazione e Strumentazione -
Elettronica Industriale, pag. 55-58, Maggio 2002.
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