Recent Advances and Prospects in ReRAM Technology - Sematech

SEMATECH Symposium Japan, 2011. 6.22
Recent Advance and Prospects in
ReRAM Technology:
Smart Electronics Application of
Functional Oxides
Hiro AKINAGA
秋永 広幸
Director Director, Innovation Innovation Center Center for for Advanced Advanced Nanodevices Nanodevices (ICAN) (ICAN)
National Institute of Advanced Industrial Science and Technology (AIST),
Tsukuba, Ibaraki 305-8569, Japan
SEMATECH Symposium Japan, 2011. 6.22
Session 6: Emerging Technologies
It’s a Smart, Dense, Functional World!
1 st Message from Akinaga
Synthetic
Material
Application for
ReRAM
Technologies
1
2

Proceedings of the IEEE, Vol. 98, No. 12 (2010)
Nanoelectronics Research: Beyond CMOS Information Processing
Nanoelectronics Research for Beyond CMOS Information Processing
BBourianoff, i ff GG. BBrillouet, ill t MM. CCavin, i RR. KK. Hi Hiramoto, t TT. HHutchby, t hb JA J. A. IIonescu, AA. M. M UUchida, hid KK.
Reference
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Brillouët, M. Bourianoff, G.I. Cavin, R.K. Hiramoto, T. Hutchby, J.A. Ionescu, A.M. Uchida, K.
In Quest of the “Next Switch”: Prospects for Greatly Reduced Power Dissipation in a Successor to the
Silicon Field-Effect Transistor
Theis, T.N. Solomon, P.M.
Carbon Nanotubes for VLSI: Interconnect and Transistor Applications
Awano, Y. Sato, S. Nihei, M. Sakai, T. Ohno, Y. Mizutani, T.
Graphene for CMOS and Beyond CMOS Applications
Banerjee, S.K. Register, L.F. Tutuc, E. Basu, D. Seyoung Kim Reddy, D. MacDonald, A.H.
III-V Nanowires—Extending a Narrowing Road
Wernersson, L.-E. Thelander, C. Lind, E. Samuelson, L.
Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems
Ricketts, D.S. Bain, J.A. Yi Luo Blanton, R.D. Mai, K. Fedder, G.K.
Mechanical Computing Redux: Relays for Integrated Circuit Applications
Pott, V. Hei Kam Nathanael, R. Jaeseok Jeon Alon, E. Tsu-Jae King Liu
Proceedings of the IEEE, Vol. 98, No. 12 (2010)
Nanoelectronics Research: Beyond CMOS Information Processing
Low-Voltage Tunnel Transistors for Beyond CMOS Logic
Seabaugh, g , A.C. Qin Zhangg
Molecular Nanoelectronics
Vuillaume, D.
Spin-Transistor Electronics: An Overview and Outlook
Sugahara, S. Nitta, J.
The Promise of Nanomagnetics and Spintronics for Future Logic and Universal Memory
Wolf, S.A. Jiwei Lu Stan, M.R. Chen, E. Treger, g D.M.
Device and Architecture Outlook for Beyond CMOS Switches
Bernstein, K. Cavin, R.K. Porod, W. Seabaugh, A. Welser, J.
Memory Devices: Energy–Space–Time Energy Space Time Tradeoffs
Zhirnov, V.V. Cavin, R.K. Menzel, S. Linn, E. Schmelzer, S. Bräuhaus, D. Schindler, C. Waser, R.
Reference
Phase Change Memory
Wong, H.P. Raoux, S. Kim, S. Liang, J. Reifenberg, J.P. Rajendran, B. Asheghi, M. Goodson, K.E.
The Atomic Switch
Aono, M. Hasegawa, T.
Resistive Random Access Memory y( (ReRAM) ) Based on Metal Oxides
Akinaga, H. Shima, H.
3
4

Recent Advance and Prospects in
ReRAM Technology
Structure
1. Brief Introduction of ReRAM
22. The mechanism of ReRAM operation* operation
3. Recent Advance in ReRAM technologies
4. Difficult Challenges and Prospects
Acknowledgement:
Dr. H. Shima (AIST)
* A part of this work was supported by NEDO.
Recent Advance and Prospects in
ReRAM Technology
Structure
1. Brief Introduction of ReRAM
22. The mechanism of ReRAM operation
3. Recent Advance in ReRAM technologies
4. Difficult Challenges and Prospects
5
6

ReRAM device structures
(a) (b) (b)
(c)
(d)
( (e) )
(d) ( (e) )
( (a) ) Typical T i l MOM simple i l stacking t ki structure t t
(b) The memory cell on the metallic via as a bottom electrode
(c) The oxidized via material for the resistance switching oxide layer
(d) The concave structure
(e) The cross-bar structure
ReRAM device operation p
nce
Resistan
IRS
LRS
HRS
0 2 4 6 8 10
RRAM is a non-volatile non volatile memory using
Switching cycle
IRS: initial resistance state
resistive changes in metal oxide; such as,
Al2O3, CoOx, CuOx, FeOx, HfO2, MgO, MnO2, NiO NiO, SiO SiO2, TO TaOx, TiO TiO2, WO WOx, ZZnO, O ZO ZrO2, SrTiO3, (Pr, Ca)MnO3 LRS: low resistance state
HRS: high resistance state
+ No additional
process load
7
8

Mg
TMOs showing g Resistive switch Al
Ti V Cr Mn Fe Co Ni Cu
Zr Nb Mo Tc Ru Rh Y Ag
Hf Ta W Re Os Ir Pt Au
NiO: S. S.Seo Seo et al., al.,APL85;M.G.Kimet APL85; M. G. Kim et al., JJAP42; S. Seo et al., APL86;
S. Seo et al., APL 87; J.-W. Park et al., J.Vac.Sci.Tech.A23;
D. C. Kim et al., APl 88; D. C. Kim et al., APL88; K. Kinoshita et al., APL89;
Y.-H. You et al., APL89, K. Tsunoda et al., IEDM2007
CoO: H. H Shima et al al., JJAP46; H. H Shima et al., al APL 91 91, HH. Shima et al., al APL93
Fe 2O 3: I. H. Inoue et al., PRB77, A. Odagawa et al., APL 91
CuxO: A. Chen et al., IEDM2005; T.-N. Fang et al., IEDM2006;,
DD. Lee et al., al IEDM2006; R. R Dong et al., al APL90
TiO x: C. Rohde et al., APL86; B. J. Choi et al., JAP98; M. Fujimoto et al., JJAP45;
K. M. Kim et al., APL89; B. J. Choi et al., APL89; K. M. Kim et al., APL90,
H. Shima et al., APL92, Y. Hosoi et al., IEDM2006
ZrO x: S. Kim et al., JJAP44; C.-Y. Lin et al., IEEE EDL28; X. Wu et al., APL90
Zn
MoOx: D. Lee et al., , APL90
x
ZnO: M. Villafuerte et al., APL90
WOx: x K.-P. Chang g et al., , SSDM2008
Nb 2O 5: H. Sim et al., Microelectronic Engineering 80;
H. Sim et al., IEEE EDL 26.
Ta 2O 5: Wei Z et al., IEDM2008
HfO x: H. Y. Lee et al., IEDM2008
MgO: Yoshida C, APL
Al 2O 3: K. M. Kim et al., Electrochemical and Solid-State Letters 9. (2004 ~ 2009)
HfO x
[1] K.-R. Kim, et al., J. Korean Phys. Soc. 59, S548 – S551 (2006). [2] H.-Y. Lee, et al., Jpn. J. Appl. Phys. 46, 2175 – 2179 (2007).
[3] M. Y. Chan, et al, Microelectric. Engineer. 85, 2420 – 2424 (2008). [4] H. Y. Lee, et al., Tech. Dig. Int. Electron Devices Meeting, San Francisco, 2008, pp. 297-300.
[5] Y.-M. Kim, and J.-S. Lee, J. Appl. Phys. 104, 114115-1 – 114115-5 (2008). [6] S. Lee, et al., J. Electrochem. Soc. 115, H92 – H96 (2008).
[7] H. Y. Lee, et al., Appl. Phys. Lett. 92, 142911-1 – 142911-3 (2008). [8] Y. S. Chen, et al., Tech. Dig. Int. Electron Devices Meeting, San Francisco, 2009, pp. 105-108.
[9] C. C Walczyk Walczyk, et al., al J. J Appl. Appl Phys. Phys 105 105, 114103-1 – 114103-6 (2009). (2009) [10] LL. Goux Goux, et al., al Electrochem Electrochem. Solid-State Lett Lett. 13 13, G54 – G56 (2010) (2010).
[11] S. Yu, et al., Electrochem. Solid-State Lett. 13, H36 – H38 (2010). [12] P.-S. Chen, et al., Jpn. J. Appl. Phys. 49, 04DD18-1 – 04DD18-5 (2010).
[13] P. Gonon, et al., J. Appl. Phys. 107, 074507-1 – 074507-9 (2010).
[14] Z. Fang, et al., Proceedings of 2010 IEEE Int. Reliability Physics Symposium, MY.4.1.-MY4.2.
9
10

I (AA)
Ti [TE] / Pr 0.7Ca Ca0.3MnO MnO 3 (100nm)
/ SrRuO3 [V(+)]
④
⑤
Forming
reverse
①
(①)
Operation Modes of ReRAM
③
②
②⇒③: SET
④⇒⑤: RESET
forward
Bipolar operation
Pt / CoO (60nm) / Pt
② ③
⑤
④
①
Forming
②⇒③: RESET
④⇒⑤: SET
Uni(Non)polar operation
● Uni-polar Operation ● Bipolar-Operation
TiN/HfO TiN/HfOx/Pt /Pt TiN/HfO TiN/HfOx/Ti/TiN /Ti/TiN
0.0010
00.0008 0008
0.0006
0.0004
0.0002
(a) TiN/HfOx/Pt
0.0005
0.0004
Forming
0.0003
R RS =10kohm = 10 kohm
0.0002
0.0001
0.0000
0 1 2 3 4 5 6
R S = 10 kohm
0.0000
0 1 2 3 4 5
I (A) )
0.0020
0.0015
00.0010 0010
0.0005
(b) TiN/HfOx/Ti
0.0005
0.0004
0.0003
0.0002
0.0001
Forming
R RS =10kohm = 10 kohm
0.0000
0 1 2 3 4
R S = 10 kohm
0.0000
-3 -2 -1 0 1 2 3
V (V)
V (V)
By changing the electrode,
both Uni-polar and Bipolar switches appear.
11
12

Resistive Switch in Pt/CoO(50nm)/Pt
I (mAA)
15
12
9
6
(a)
Pt/Co-O/Pt
1st sweep p( (Forming) g)
2nd sweep (Reset: LRS→ HRS)
3rd sweep (Set HRS→LRS)
3 R S = 910 Ω
0
0 2 4
V (V)
6 8 10
I (mAA)
By increasing the Set current,
from Memory to Threshold switch.
100
80
60
40
20
0
Pt/Co-O/Pt
R = 120 Ω
S
1st sweep
2nd sweep
3rd sweep
(b)
0 1 2 3 4
V (V)
Series R S
H. Shima and Y. Tamai, Microelectronics Journal 40, 628 (2009).
Wh Why RReRAM? RAM?
RRAM
□□, CMOS compatibility tibilit ( (materials, t i l process…) )
□, No physical scaling limit, < 5 [nm]
strong competitiveness in price / recording-bit
□□, Ultra-fast Ultra fast operation, operation < 10 [ns]
□, low-power operation, < 10 [μA]
□, (tolerably) high endurance, ~ 109 11 9~11 R/W
□, (tolerably) good retention, ~ 150 ℃
□, Large ON / OFF ratio, ~ 103 ( y) g
□□, Flexible application to various devices
13
14

Recent Advance and Prospects in
ReRAM Technology
Structure
1. Brief Introduction of ReRAM
22. The mechanism of ReRAM operation
3. Recent Advance in ReRAM technologies
4. Difficult Challenges and Prospects
ReRAM operation mechanism
Correction of misapprehension about
the operation mechanism of binary-metal-oxide ReRAM
Filament model (Fuse-Antifuse operation)
vs ( (conflicting) fli ti )
Interface model
(incl. Schottky Barrier height modulation)
15
16

Operation mechanism of ReRAM
oxidation id ti
V+
reduction GND
Soft breakdown
Off state
(High ( g Resistance State) )
SET (Forming)
Initial state
RESET
~ 30 nm
> 50 nm
Anodic
oxidization
Operation mechanism of ReRAM
oxidation id ti
V+
reduction GND
Soft breakdown
Off state
(High ( g Resistance State) )
V+
GND
V-
GND
SET (Forming)
Initial state
RESET
~ 30 nm
> 50 nm
Anodic
oxidization
Next Page!
V+
GND
V-
GND
On state
(Low ( Resistance State) )
Virtual cathode
17
On state
(Low ( Resistance State) )
Virtual cathode
18

Operation p mechanism of ReRAM (beyond ( y 2X nm generation)
g )
Electrode
Oxygen supplier/
Reservoir
Oxide layer
(R switching) i hi )
Electrode
Oxygen yg ions
Off state (HRS)
~ 5 nm
~ 5 nm
SET (Forming)
RESET
V+
GND
V-
GND
On state (LRS)
Conductive
(defect/vacancy)
In the nano-meter ReRAM device, the filament model does NOT conflict
with ith th the iinterface t f model. d l Th The electrochemical l t h i l reaction ti at t the th iinterface t f
brings about the non-volatile resistance switching.
Unified model of ReRAM operation p (beyond ( y 2X nm generation)
g )
Electrode
Oxygen supplier/
Reservoir
Oxide layer
(R switching) i hi )
Electrode
Oxygen yg ions
Off state (HRS)
SMART!!
SET (Forming)
V+
RESET
GND
V-
GND
On state (LRS)
Conductive
(defect/vacancy)
In the nano-meter ReRAM device, the filament model does NOT conflict
with ith th the iinterface t f model. d l Th The electrochemical l t h i l reaction ti at t the th iinterface t f
brings about the non-volatile resistance switching.
19
20

Operation p mechanism of ReRAM Key y points:
The Reset current (Active cell size)
will be determined by the Set current.
Controlled by SET current
(High Resistivity)
Decrease in SET current
Key issues: issues To select proper combination of the electrode and the oxide layer
We can control the active cell size at will in the operation.
Operation p mechanism of ReRAM
SSoft ft bbreakdown kd CCurrent-induced t i d d oxidation id ti
driven by the electric field
Key points:
The Reset current (Active ( cell size) )
will be determined by the Set current.
Key issues: issues To select proper combination of the electrode and the oxide layer
We can control the active cell size, even beyond 2X nm generation!
21
22

2.5
Vooltage
(VV)
Demonstration of Fast & Low-power operation
2.0
achieved by selecting the combination of Ta and CoO
to fabricate the electrochemically active interface.
250
200
15 1.5
150
1.0
100
05 0.5
50
0
0
-0.5 0.5
0 50 100 150
-50 50
200
Time (ns)
Cuurrent
(μμA)
Vooltage
(VV)
0.5
50
0
0
-0.5 05
-50 50
-1.0
-100
-1 -1.55
-150
-2.0
-200
-2.5
0 50 100 150
-250 250
200
Time (ns)
Fig Fig. 4 Applied pulse voltage and writing current waveforms of Ta/CoO/Pt for
(a) Set and (b) Reset. Set and reset conditions are 2.2 V 50 ns and -1.4 V 50 ns,
respectively.
2008 IInternational t ti l CConference f on SSolid lid St State t DDevices i and d MMaterials t i l (SSDM 2008) 2008).
Date : September 23-26, 2008
RESET current is controlled
by SET operation
(μA)
Current C
Important Issues for ReRAM Circuit (TEG) Design
② ③
⑤
④
①
Forming
②⇒③: RESET
④⇒⑤: SET
NVM operation without
Forming process, by
controlling the thicknesses of
the oxide layer y and the
metal electrode, and/or PTA
The current compliance is
controlled by the transistor
(by a diode in the future)
23
24

Recent Advance and Prospects in
ReRAM Technology
Structure
1. Brief Introduction of ReRAM
22. The mechanism of ReRAM operation
3. Recent Advance in ReRAM technologies
4. Difficult Challenges and Prospects
SRC/NSF/A*STAR Forum on 2020 Semiconductor Memory Strategies: Processes, Devices, and Architectures,
Hiro AKINAGA and Hisashi SHIMA, Oct. 20-21, 2009, Singapore
An example of importance to control the interface
Coounts
25
20
15
10
5
As prepared
Forming voltage VF Pt/CoO(10nm)/PtTE
n = 24
20 x 20 um 2
After
EB蒸着 interface PtTEcontrol
TE drive
Before スパッタ PtTE
interface (ULVAC) control
0
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
V F (V)
Forming (1st SET) voltage and current (not shown)
are stabilized by the interface control
25
26

TSSC
(pA)
MRS 2010 Fall Meeting Symposium K (K8.20)
TE deposition process dependence of TSC
2 2
10 2
10 2
10 1
10 0
10 -1
10 -2
10 2
(a) SPT-RRAM
TSSC
(pA)
10 1
10 0
10 -1
10 -2
10 2
(b) EB-RRAM
50 100 150 200 250 50 100 150 200 250
T (K)
T (K)
Temperature p ( (T) ) dependence p of TSC ( (thermally y stimulated
current) in (a) SPT-RRAM and (b) EB-RRAM devices. On the T Tm (K) E ( (eV) V)
whole, the T dependence of TSC in SPT-RRAM is gentle over
a wide temperature range. Three distinguishing peaks in TSC A 112 0.20
were confirmed for EB EB-RRAM RRAM as depicted by the blue arrows arrows.
This indicates the existence of tightly distributed energy levels
B 165 00.32 32
in EB-RRAM.
4
E = kBTm
ln( Tm
/ β )
C 220 0.44
* M.G. Buehler, Solid State Electron. 15, (1972) 69
*
kB: Boltzmann constant
β: Temperature ramping rate(0.15K/sec)
Forming process in RVS test
I-t curve in CVS test
t tBD di distribution t ib ti in i CVS test t t
T dependence of TSC
A
MRS 2010 Fall Meeting Symposium K (K8.20)
B
EB EB-RRAM RRAM SPT SPT-RRAM RRAM
Smaller VF and IF Larger VF and IF distributions distributions
Spiky noise observed A monotonic change
Smaller especially p y
for small VCVS LLarger
Peaks observed A monotonic change
EB-RRAM SPT-RRAM The trap levels which dominate the
Carrier Carrier
current condition during the forming
(breakdown) process are affected by
the TE deposition process. In EB-RRAM,
more tightly distributed trap levels exists
in the device homogeneously. g y On the
other hands, trap levels induced by the
TE deposition process increases the
randomness of the breakdown process.
C
27
28

Recent Advance and Prospects in
ReRAM Technology
Structure
1. Brief Introduction of ReRAM
22. The mechanism of ReRAM operation
3. Recent Advance in ReRAM technologies
4. Difficult Challenges and Prospects
currennt
Operating
Operating current and speed in ReRAM
10mA
1mA
100μA μ
10μA
H. Y. Lee et al.,
ITRI
< 25 μAA IEDM2008
K. Tsunoda
et a al.,Fujitsu , uj tsu
IEDM2007
Z. Wei et al.,
Panasonic,
IEDM2008
Y. Hosoi et al., ,
SHARP&AIST,
IEDM2006
High speed
operation
LLow current t operation ti
YY. Tamai et al al.,
SHARP & AIST
SSDM2008
S. E. Ahn et al.,
Samsung,
Adv. Mater 2008
I. G. Baek et al.,
Samsung,
IEDM2004
1ns 10ns 100ns 1μs μ 10μs μ
Operating speed
29
30

I. G. Baek et al.,
Samsung,
IEDM2004
Cyccle
enduurance
Current C ( μA)
10 10
10 3
10 2
10 1
Comparison with MOSFET drive current
Y. Hosoi et al.,
SHARP&AIST
SHARP&AIST,
IEDM2006
Z. Wei et al.,
Panasonic, a aso c,
IEDM2008
K. Tsunoda
et al.,Fujitsu
IEDM2007
NMOS ddrive i current t
(ITRS2007, Low operating power technology)
for gate width of 100 nm
Planar bulk
UTB FD
These NMOS drive current
DG
was calculated for the gate
width of 100 nm.
Y. Tamai et al.,
SHARP & AIST
SSDM2008
S. E. Ahn et al.,
Samsung,
Adv. Mater 2008
H. Y. Lee et al.,
ITRI
IEDM2008
Operating current of ReRAM
can be lower than the MOSFET
drive current, indicating that
ReRAM is appropriate ffor
the
low operating power technology.
2002 2004 2006 2008 2010 2012 2014 2016
Calendar year
:Pt free devices
Cycle y endurance ( (CE) )
10 11
10 12
10
H. Y. Lee et al.,
IEDM2010
Estimation on
required cycle endurance:
11 Z. Wei et al.,
IEDM2010
Technical program
required cycle endurance:
IEDM2008(Pt/Ta2O5/Pt)
(19.7), HfOx-RRAM
10 9
10 8
10 7
10 6
10
10 5
HH. YY. LLee et t al, l IEDM2008
(TiN/HfOx/Ti/TiN)
Samsung
ITRI
C. Yoshida et al,
APL2007(Pt/TiOx/TiN)
Fujitsu
I. G. Baek et al.,
IEDM2004(Pt/NiO/Pt)
Panasonic
ITRI
NEC
H. Y. Lee et al, JJAP
(TiN/HfO (TiN/HfOx/Ti/TiN) /Ti/TiN)
M. Terai et al,IEDM2009
(BE/TiOx/Ta2O5/Pt) ITRI
ITRI
H. Y. Lee et al, JJAP
(TiN/HfOx/Ta)
• Writing frequency: 1Hz
(1 time / 1 sec)
• A period of use: 1 yrs
31
= 3.1 x 10 7 sec
A practical CE for 1 memory
element is in the order of
10 7 times.
CE in RRAM exceeds
current Flash memories
National Tsin-Hua University
10 4 y
Y. H. Zheng, et al,
CE for single bit
IEDM2009 (Si/SiO2/TiON/TiN/W)
Flash memory
10 3
2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014
Calendar Year
CE for multi multi-bit bit
Flash memory
32

Pt
Ti
HfO x
Nanoscale characterization of oxides
Integrated EEELS
signal
30000
25000
20000
15000
10000
5000
BE (a) TE (b)
Pt(BE)/HfO x /Ti(5nm)/Pt
Ti-L (PDA)
O-K (PDA)
O-K (PDA)
Ti-L (PDA)
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Relative position
Pt
•Electron energy loss spectroscopy (EELS) is a powerful
tool to characterize oxides with a nanoscale resolution.
However, , especially p y for the high-k g oxide such as HfOx, ,
the characterization of Hf edge becomes difficult
HADEF-STEM image of HfOx/Ti interface because of the severe signal intensity decay.
Development of nanoscale metrology for RRAM is
crucial in order to improve the operating reliability of
RRAM in association with the material characteristics.
Possible Role-sharing of ReRAM
CPU
~ 1ns
Cache
~5ns
DRAM ~
10ns
NAND (SSD)
HDD
ReRAM
(1) Non-volatile
(2) ( ) Byte y Access
(3) Fast operation (~10ns)
1st Target:
To solve I/O bottleneck
33
34

Recent Advance and Prospects in
ReRAM Technology
2 nd Message from Akinaga
ReRAM technology is very young (< 10 years), but
Many y similarities between High-k g and ReRAM technologies g
We need…
1. Knowledge of Solid State Chemistry in Semicond. Tech.
22. Further advance metrology for nano-scale devices
3. Conversation with researchers of emerging architecture
35
36

cherry on the cake…..
Standard Semiconductor Technology
carrier doping
37
38

Mott Transition FET(Mott ( Transistor) )
carrier doping
(filling control)
MMott ttI Insulator l t Mtl Metal
·A large number of electrons are Localized electrons become
localized due to electron correlation correlation. itinerant by carrier doping. doping
Sh Schematics ti of felectric l ti double d blllayer ttransistor it (EDLT)
Source
~1nm EDL
anion (BF (BF4) )
+ + + +
NSNO Channel
Drain
Size of the channel 10 μmØ 100 μm
Ionic Liquid: DEME-BF 4
Ionic Liquid
(Electrolyte)
cation
(DEME)
separator p Au/Pt Gate
NdGaO 3
10 10μF/cm F/ 2@10 3H 2@10-3Hz →1.5 × 1014 hole/cm2@VG=-2.5 39
40

NdNiO 3 Channel
-2.5 0 Vgs (V)
Acknowledgement: M. Kawasaki and Y. Iwasa
Nonvolatile Diode Switch
Substrate
PtTE
TiO x
PtBE
Fig.1 Schematic Illustration of the Pt/TiO x/Pt Diode.
Recently, an novel nonvolatile switch
behavior has been successfully
demonstrated in a simple sandwich
Pt/TiOx/Pt (Fig.1) structure by our group.
After applying a negative pulse voltage, the
forward current was observed in the
negative bias (Fig (Fig.2). 2) It demonstrates that
the diode polarity was switched. The
reproducible switch behavior was
successfully demonstrated (Fig.3).
H. Shima, N. Zhong, H. Akinaga, Appl. Phys. Lett. 94, 082905 (2009).
N. Zhong, H. Shima, H. Akinaga, Jpn. J. Appl. Phys 48, 05DF03 (2009).
Asanuma et al., APL 97, 142110 (2010).
(a)
(b)
Fig. 2 Current-voltage (I-V ) curves of Pt/TiOx/Pt (a)initial state (b) after applying voltage pulse pulse.
(a) (b)
Fig.3 Current-voltage curves of Pt/TiO x/Pt following the
voltage pulse application of (a) h/w=-6.0V/900ms and (b)
h/w=+6.0V/900ms.
41
42

Mechanism of the nonvolatile diode switch
(a)
(b)
PtTE
V VO V VO TiO x
V VO V VO VO VO VO PtBE
V O
φ b
w
Pt TiO x (high ( g
x)
+ -
(c) ( w
(c) )
φb Pt TiOx (low
x)
- +
Fig. 4 (a) Profile of VO in virgin Pt/TiOx/Pt; band structure
and equivalent circuit of TiOx/Pt interface [TiOx: (b)
stoichiometriclike and (c) heavily reduced] reduced].
(a)
PtTE
V O
V O
TiO x
VO VO VO VO VO PtBE
(b)
PtTE
VO VO VO VO VO TiO x
V O
V O
PtBE
Fig. 5 Profile of V O in Pt/TiO x/Pt and equivalent circuit of
TiO x/Pt interface TiO x. (a) initial state or after applying positive
pulse voltage; (b) after applying negative pulse voltage.
As shown in Fig.4, it is assumed that an intrinsic-dead layer is produced at the beginning of
the deposition processing, which contributes to the Ohmic contact of BE/TiO x, due to a good
many of the defects in this intrinsic-dead layer. For TiO x/TE interface, the interface state is
controlled by the deposition condition. High O2 partial pressure results in low concentration of
the defects in TiOx layer, therefore, a Schottky barrier would be obtained.
As shown in Fig. 5, the nonvolatile switching is proposed to be originated from the electrical
control of the chemical state in TiO TiOx such as the oxygen vacancy concentration at the
interfaces between the TiO x layer and Pt electrodes. H. Shima, N. Zhong, H. Akinaga, Appl. Phys. Lett. 94, 082905 (2009).
N. Zhong, H. Shima, H. Akinaga, Appl. Phys. Lett. 96, 042107 (2010).
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