Recent Advances and Prospects in ReRAM Technology - Sematech
Recent Advances and Prospects in ReRAM Technology - Sematech
Recent Advances and Prospects in ReRAM Technology - Sematech
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SEMATECH Symposium Japan, 2011. 6.22<br />
<strong>Recent</strong> Advance <strong>and</strong> <strong>Prospects</strong> <strong>in</strong><br />
<strong>ReRAM</strong> <strong>Technology</strong>:<br />
Smart Electronics Application of<br />
Functional Oxides<br />
Hiro AKINAGA<br />
秋永 広幸<br />
Director Director, Innovation Innovation Center Center for for Advanced Advanced Nanodevices Nanodevices (ICAN) (ICAN)<br />
National Institute of Advanced Industrial Science <strong>and</strong> <strong>Technology</strong> (AIST),<br />
Tsukuba, Ibaraki 305-8569, Japan<br />
SEMATECH Symposium Japan, 2011. 6.22<br />
Session 6: Emerg<strong>in</strong>g Technologies<br />
It’s a Smart, Dense, Functional World!<br />
1 st Message from Ak<strong>in</strong>aga<br />
Synthetic<br />
Material<br />
Application for<br />
<strong>ReRAM</strong><br />
Technologies<br />
1<br />
2
Proceed<strong>in</strong>gs of the IEEE, Vol. 98, No. 12 (2010)<br />
Nanoelectronics Research: Beyond CMOS Information Process<strong>in</strong>g<br />
Nanoelectronics Research for Beyond CMOS Information Process<strong>in</strong>g<br />
BBourianoff, i ff GG. BBrillouet, ill t MM. CCav<strong>in</strong>, i RR. KK. Hi Hiramoto, t TT. HHutchby, t hb JA J. A. IIonescu, AA. M. M UUchida, hid KK.<br />
Reference<br />
Regional, National, <strong>and</strong> International Nanoelectronics Research Programs: Topical Concentration <strong>and</strong> Gaps<br />
Brillouët, M. Bourianoff, G.I. Cav<strong>in</strong>, R.K. Hiramoto, T. Hutchby, J.A. Ionescu, A.M. Uchida, K.<br />
In Quest of the “Next Switch”: <strong>Prospects</strong> for Greatly Reduced Power Dissipation <strong>in</strong> a Successor to the<br />
Silicon Field-Effect Transistor<br />
Theis, T.N. Solomon, P.M.<br />
Carbon Nanotubes for VLSI: Interconnect <strong>and</strong> Transistor Applications<br />
Awano, Y. Sato, S. Nihei, M. Sakai, T. Ohno, Y. Mizutani, T.<br />
Graphene for CMOS <strong>and</strong> Beyond CMOS Applications<br />
Banerjee, S.K. Register, L.F. Tutuc, E. Basu, D. Seyoung Kim Reddy, D. MacDonald, A.H.<br />
III-V Nanowires—Extend<strong>in</strong>g a Narrow<strong>in</strong>g Road<br />
Wernersson, L.-E. Thel<strong>and</strong>er, C. L<strong>in</strong>d, E. Samuelson, L.<br />
Enhanc<strong>in</strong>g CMOS Us<strong>in</strong>g Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems<br />
Ricketts, D.S. Ba<strong>in</strong>, J.A. Yi Luo Blanton, R.D. Mai, K. Fedder, G.K.<br />
Mechanical Comput<strong>in</strong>g Redux: Relays for Integrated Circuit Applications<br />
Pott, V. Hei Kam Nathanael, R. Jaeseok Jeon Alon, E. Tsu-Jae K<strong>in</strong>g Liu<br />
Proceed<strong>in</strong>gs of the IEEE, Vol. 98, No. 12 (2010)<br />
Nanoelectronics Research: Beyond CMOS Information Process<strong>in</strong>g<br />
Low-Voltage Tunnel Transistors for Beyond CMOS Logic<br />
Seabaugh, g , A.C. Q<strong>in</strong> Zhangg<br />
Molecular Nanoelectronics<br />
Vuillaume, D.<br />
Sp<strong>in</strong>-Transistor Electronics: An Overview <strong>and</strong> Outlook<br />
Sugahara, S. Nitta, J.<br />
The Promise of Nanomagnetics <strong>and</strong> Sp<strong>in</strong>tronics for Future Logic <strong>and</strong> Universal Memory<br />
Wolf, S.A. Jiwei Lu Stan, M.R. Chen, E. Treger, g D.M.<br />
Device <strong>and</strong> Architecture Outlook for Beyond CMOS Switches<br />
Bernste<strong>in</strong>, K. Cav<strong>in</strong>, R.K. Porod, W. Seabaugh, A. Welser, J.<br />
Memory Devices: Energy–Space–Time Energy Space Time Tradeoffs<br />
Zhirnov, V.V. Cav<strong>in</strong>, R.K. Menzel, S. L<strong>in</strong>n, E. Schmelzer, S. Bräuhaus, D. Sch<strong>in</strong>dler, C. Waser, R.<br />
Reference<br />
Phase Change Memory<br />
Wong, H.P. Raoux, S. Kim, S. Liang, J. Reifenberg, J.P. Rajendran, B. Asheghi, M. Goodson, K.E.<br />
The Atomic Switch<br />
Aono, M. Hasegawa, T.<br />
Resistive R<strong>and</strong>om Access Memory y( (<strong>ReRAM</strong>) ) Based on Metal Oxides<br />
Ak<strong>in</strong>aga, H. Shima, H.<br />
3<br />
4
<strong>Recent</strong> Advance <strong>and</strong> <strong>Prospects</strong> <strong>in</strong><br />
<strong>ReRAM</strong> <strong>Technology</strong><br />
Structure<br />
1. Brief Introduction of <strong>ReRAM</strong><br />
22. The mechanism of <strong>ReRAM</strong> operation* operation<br />
3. <strong>Recent</strong> Advance <strong>in</strong> <strong>ReRAM</strong> technologies<br />
4. Difficult Challenges <strong>and</strong> <strong>Prospects</strong><br />
Acknowledgement:<br />
Dr. H. Shima (AIST)<br />
* A part of this work was supported by NEDO.<br />
<strong>Recent</strong> Advance <strong>and</strong> <strong>Prospects</strong> <strong>in</strong><br />
<strong>ReRAM</strong> <strong>Technology</strong><br />
Structure<br />
1. Brief Introduction of <strong>ReRAM</strong><br />
22. The mechanism of <strong>ReRAM</strong> operation<br />
3. <strong>Recent</strong> Advance <strong>in</strong> <strong>ReRAM</strong> technologies<br />
4. Difficult Challenges <strong>and</strong> <strong>Prospects</strong><br />
5<br />
6
<strong>ReRAM</strong> device structures<br />
(a) (b) (b)<br />
(c)<br />
(d)<br />
( (e) )<br />
(d) ( (e) )<br />
( (a) ) Typical T i l MOM simple i l stack<strong>in</strong>g t ki structure t t<br />
(b) The memory cell on the metallic via as a bottom electrode<br />
(c) The oxidized via material for the resistance switch<strong>in</strong>g oxide layer<br />
(d) The concave structure<br />
(e) The cross-bar structure<br />
<strong>ReRAM</strong> device operation p<br />
nce<br />
Resistan<br />
IRS<br />
LRS<br />
HRS<br />
0 2 4 6 8 10<br />
RRAM is a non-volatile non volatile memory us<strong>in</strong>g<br />
Switch<strong>in</strong>g cycle<br />
IRS: <strong>in</strong>itial resistance state<br />
resistive changes <strong>in</strong> metal oxide; such as,<br />
Al2O3, CoOx, CuOx, FeOx, HfO2, MgO, MnO2, NiO NiO, SiO SiO2, TO TaOx, TiO TiO2, WO WOx, ZZnO, O ZO ZrO2, SrTiO3, (Pr, Ca)MnO3 LRS: low resistance state<br />
HRS: high resistance state<br />
+ No additional<br />
process load<br />
7<br />
8
Mg<br />
TMOs show<strong>in</strong>g g Resistive switch Al<br />
Ti V Cr Mn Fe Co Ni Cu<br />
Zr Nb Mo Tc Ru Rh Y Ag<br />
Hf Ta W Re Os Ir Pt Au<br />
NiO: S. S.Seo Seo et al., al.,APL85;M.G.Kimet APL85; M. G. Kim et al., JJAP42; S. Seo et al., APL86;<br />
S. Seo et al., APL 87; J.-W. Park et al., J.Vac.Sci.Tech.A23;<br />
D. C. Kim et al., APl 88; D. C. Kim et al., APL88; K. K<strong>in</strong>oshita et al., APL89;<br />
Y.-H. You et al., APL89, K. Tsunoda et al., IEDM2007<br />
CoO: H. H Shima et al al., JJAP46; H. H Shima et al., al APL 91 91, HH. Shima et al., al APL93<br />
Fe 2O 3: I. H. Inoue et al., PRB77, A. Odagawa et al., APL 91<br />
CuxO: A. Chen et al., IEDM2005; T.-N. Fang et al., IEDM2006;,<br />
DD. Lee et al., al IEDM2006; R. R Dong et al., al APL90<br />
TiO x: C. Rohde et al., APL86; B. J. Choi et al., JAP98; M. Fujimoto et al., JJAP45;<br />
K. M. Kim et al., APL89; B. J. Choi et al., APL89; K. M. Kim et al., APL90,<br />
H. Shima et al., APL92, Y. Hosoi et al., IEDM2006<br />
ZrO x: S. Kim et al., JJAP44; C.-Y. L<strong>in</strong> et al., IEEE EDL28; X. Wu et al., APL90<br />
Zn<br />
MoOx: D. Lee et al., , APL90<br />
x<br />
ZnO: M. Villafuerte et al., APL90<br />
WOx: x K.-P. Chang g et al., , SSDM2008<br />
Nb 2O 5: H. Sim et al., Microelectronic Eng<strong>in</strong>eer<strong>in</strong>g 80;<br />
H. Sim et al., IEEE EDL 26.<br />
Ta 2O 5: Wei Z et al., IEDM2008<br />
HfO x: H. Y. Lee et al., IEDM2008<br />
MgO: Yoshida C, APL<br />
Al 2O 3: K. M. Kim et al., Electrochemical <strong>and</strong> Solid-State Letters 9. (2004 ~ 2009)<br />
HfO x<br />
[1] K.-R. Kim, et al., J. Korean Phys. Soc. 59, S548 – S551 (2006). [2] H.-Y. Lee, et al., Jpn. J. Appl. Phys. 46, 2175 – 2179 (2007).<br />
[3] M. Y. Chan, et al, Microelectric. Eng<strong>in</strong>eer. 85, 2420 – 2424 (2008). [4] H. Y. Lee, et al., Tech. Dig. Int. Electron Devices Meet<strong>in</strong>g, San Francisco, 2008, pp. 297-300.<br />
[5] Y.-M. Kim, <strong>and</strong> J.-S. Lee, J. Appl. Phys. 104, 114115-1 – 114115-5 (2008). [6] S. Lee, et al., J. Electrochem. Soc. 115, H92 – H96 (2008).<br />
[7] H. Y. Lee, et al., Appl. Phys. Lett. 92, 142911-1 – 142911-3 (2008). [8] Y. S. Chen, et al., Tech. Dig. Int. Electron Devices Meet<strong>in</strong>g, San Francisco, 2009, pp. 105-108.<br />
[9] C. C Walczyk Walczyk, et al., al J. J Appl. Appl Phys. Phys 105 105, 114103-1 – 114103-6 (2009). (2009) [10] LL. Goux Goux, et al., al Electrochem Electrochem. Solid-State Lett Lett. 13 13, G54 – G56 (2010) (2010).<br />
[11] S. Yu, et al., Electrochem. Solid-State Lett. 13, H36 – H38 (2010). [12] P.-S. Chen, et al., Jpn. J. Appl. Phys. 49, 04DD18-1 – 04DD18-5 (2010).<br />
[13] P. Gonon, et al., J. Appl. Phys. 107, 074507-1 – 074507-9 (2010).<br />
[14] Z. Fang, et al., Proceed<strong>in</strong>gs of 2010 IEEE Int. Reliability Physics Symposium, MY.4.1.-MY4.2.<br />
9<br />
10
I (AA)<br />
Ti [TE] / Pr 0.7Ca Ca0.3MnO MnO 3 (100nm)<br />
/ SrRuO3 [V(+)]<br />
④<br />
⑤<br />
Form<strong>in</strong>g<br />
reverse<br />
①<br />
(①)<br />
Operation Modes of <strong>ReRAM</strong><br />
③<br />
②<br />
②⇒③: SET<br />
④⇒⑤: RESET<br />
forward<br />
Bipolar operation<br />
Pt / CoO (60nm) / Pt<br />
② ③<br />
⑤<br />
④<br />
①<br />
Form<strong>in</strong>g<br />
②⇒③: RESET<br />
④⇒⑤: SET<br />
Uni(Non)polar operation<br />
● Uni-polar Operation ● Bipolar-Operation<br />
TiN/HfO TiN/HfOx/Pt /Pt TiN/HfO TiN/HfOx/Ti/TiN /Ti/TiN<br />
0.0010<br />
00.0008 0008<br />
0.0006<br />
0.0004<br />
0.0002<br />
(a) TiN/HfOx/Pt<br />
0.0005<br />
0.0004<br />
Form<strong>in</strong>g<br />
0.0003<br />
R RS =10kohm = 10 kohm<br />
0.0002<br />
0.0001<br />
0.0000<br />
0 1 2 3 4 5 6<br />
R S = 10 kohm<br />
0.0000<br />
0 1 2 3 4 5<br />
I (A) )<br />
0.0020<br />
0.0015<br />
00.0010 0010<br />
0.0005<br />
(b) TiN/HfOx/Ti<br />
0.0005<br />
0.0004<br />
0.0003<br />
0.0002<br />
0.0001<br />
Form<strong>in</strong>g<br />
R RS =10kohm = 10 kohm<br />
0.0000<br />
0 1 2 3 4<br />
R S = 10 kohm<br />
0.0000<br />
-3 -2 -1 0 1 2 3<br />
V (V)<br />
V (V)<br />
By chang<strong>in</strong>g the electrode,<br />
both Uni-polar <strong>and</strong> Bipolar switches appear.<br />
11<br />
12
Resistive Switch <strong>in</strong> Pt/CoO(50nm)/Pt<br />
I (mAA)<br />
15<br />
12<br />
9<br />
6<br />
(a)<br />
Pt/Co-O/Pt<br />
1st sweep p( (Form<strong>in</strong>g) g)<br />
2nd sweep (Reset: LRS→ HRS)<br />
3rd sweep (Set HRS→LRS)<br />
3 R S = 910 Ω<br />
0<br />
0 2 4<br />
V (V)<br />
6 8 10<br />
I (mAA)<br />
By <strong>in</strong>creas<strong>in</strong>g the Set current,<br />
from Memory to Threshold switch.<br />
100<br />
80<br />
60<br />
40<br />
20<br />
0<br />
Pt/Co-O/Pt<br />
R = 120 Ω<br />
S<br />
1st sweep<br />
2nd sweep<br />
3rd sweep<br />
(b)<br />
0 1 2 3 4<br />
V (V)<br />
Series R S<br />
H. Shima <strong>and</strong> Y. Tamai, Microelectronics Journal 40, 628 (2009).<br />
Wh Why R<strong>ReRAM</strong>? RAM?<br />
RRAM<br />
□□, CMOS compatibility tibilit ( (materials, t i l process…) )<br />
□, No physical scal<strong>in</strong>g limit, < 5 [nm]<br />
strong competitiveness <strong>in</strong> price / record<strong>in</strong>g-bit<br />
□□, Ultra-fast Ultra fast operation, operation < 10 [ns]<br />
□, low-power operation, < 10 [μA]<br />
□, (tolerably) high endurance, ~ 109 11 9~11 R/W<br />
□, (tolerably) good retention, ~ 150 ℃<br />
□, Large ON / OFF ratio, ~ 103 ( y) g<br />
□□, Flexible application to various devices<br />
13<br />
14
<strong>Recent</strong> Advance <strong>and</strong> <strong>Prospects</strong> <strong>in</strong><br />
<strong>ReRAM</strong> <strong>Technology</strong><br />
Structure<br />
1. Brief Introduction of <strong>ReRAM</strong><br />
22. The mechanism of <strong>ReRAM</strong> operation<br />
3. <strong>Recent</strong> Advance <strong>in</strong> <strong>ReRAM</strong> technologies<br />
4. Difficult Challenges <strong>and</strong> <strong>Prospects</strong><br />
<strong>ReRAM</strong> operation mechanism<br />
Correction of misapprehension about<br />
the operation mechanism of b<strong>in</strong>ary-metal-oxide <strong>ReRAM</strong><br />
Filament model (Fuse-Antifuse operation)<br />
vs ( (conflict<strong>in</strong>g) fli ti )<br />
Interface model<br />
(<strong>in</strong>cl. Schottky Barrier height modulation)<br />
15<br />
16
Operation mechanism of <strong>ReRAM</strong><br />
oxidation id ti<br />
V+<br />
reduction GND<br />
Soft breakdown<br />
Off state<br />
(High ( g Resistance State) )<br />
SET (Form<strong>in</strong>g)<br />
Initial state<br />
RESET<br />
~ 30 nm<br />
> 50 nm<br />
Anodic<br />
oxidization<br />
Operation mechanism of <strong>ReRAM</strong><br />
oxidation id ti<br />
V+<br />
reduction GND<br />
Soft breakdown<br />
Off state<br />
(High ( g Resistance State) )<br />
V+<br />
GND<br />
V-<br />
GND<br />
SET (Form<strong>in</strong>g)<br />
Initial state<br />
RESET<br />
~ 30 nm<br />
> 50 nm<br />
Anodic<br />
oxidization<br />
Next Page!<br />
V+<br />
GND<br />
V-<br />
GND<br />
On state<br />
(Low ( Resistance State) )<br />
Virtual cathode<br />
17<br />
On state<br />
(Low ( Resistance State) )<br />
Virtual cathode<br />
18
Operation p mechanism of <strong>ReRAM</strong> (beyond ( y 2X nm generation)<br />
g )<br />
Electrode<br />
Oxygen supplier/<br />
Reservoir<br />
Oxide layer<br />
(R switch<strong>in</strong>g) i hi )<br />
Electrode<br />
Oxygen yg ions<br />
Off state (HRS)<br />
~ 5 nm<br />
~ 5 nm<br />
SET (Form<strong>in</strong>g)<br />
RESET<br />
V+<br />
GND<br />
V-<br />
GND<br />
On state (LRS)<br />
Conductive<br />
(defect/vacancy)<br />
In the nano-meter <strong>ReRAM</strong> device, the filament model does NOT conflict<br />
with ith th the i<strong>in</strong>terface t f model. d l Th The electrochemical l t h i l reaction ti at t the th i<strong>in</strong>terface t f<br />
br<strong>in</strong>gs about the non-volatile resistance switch<strong>in</strong>g.<br />
Unified model of <strong>ReRAM</strong> operation p (beyond ( y 2X nm generation)<br />
g )<br />
Electrode<br />
Oxygen supplier/<br />
Reservoir<br />
Oxide layer<br />
(R switch<strong>in</strong>g) i hi )<br />
Electrode<br />
Oxygen yg ions<br />
Off state (HRS)<br />
SMART!!<br />
SET (Form<strong>in</strong>g)<br />
V+<br />
RESET<br />
GND<br />
V-<br />
GND<br />
On state (LRS)<br />
Conductive<br />
(defect/vacancy)<br />
In the nano-meter <strong>ReRAM</strong> device, the filament model does NOT conflict<br />
with ith th the i<strong>in</strong>terface t f model. d l Th The electrochemical l t h i l reaction ti at t the th i<strong>in</strong>terface t f<br />
br<strong>in</strong>gs about the non-volatile resistance switch<strong>in</strong>g.<br />
19<br />
20
Operation p mechanism of <strong>ReRAM</strong> Key y po<strong>in</strong>ts:<br />
The Reset current (Active cell size)<br />
will be determ<strong>in</strong>ed by the Set current.<br />
Controlled by SET current<br />
(High Resistivity)<br />
Decrease <strong>in</strong> SET current<br />
Key issues: issues To select proper comb<strong>in</strong>ation of the electrode <strong>and</strong> the oxide layer<br />
We can control the active cell size at will <strong>in</strong> the operation.<br />
Operation p mechanism of <strong>ReRAM</strong><br />
SSoft ft bbreakdown kd CCurrent-<strong>in</strong>duced t i d d oxidation id ti<br />
driven by the electric field<br />
Key po<strong>in</strong>ts:<br />
The Reset current (Active ( cell size) )<br />
will be determ<strong>in</strong>ed by the Set current.<br />
Key issues: issues To select proper comb<strong>in</strong>ation of the electrode <strong>and</strong> the oxide layer<br />
We can control the active cell size, even beyond 2X nm generation!<br />
21<br />
22
2.5<br />
Vooltage<br />
(VV)<br />
Demonstration of Fast & Low-power operation<br />
2.0<br />
achieved by select<strong>in</strong>g the comb<strong>in</strong>ation of Ta <strong>and</strong> CoO<br />
to fabricate the electrochemically active <strong>in</strong>terface.<br />
250<br />
200<br />
15 1.5<br />
150<br />
1.0<br />
100<br />
05 0.5<br />
50<br />
0<br />
0<br />
-0.5 0.5<br />
0 50 100 150<br />
-50 50<br />
200<br />
Time (ns)<br />
Cuurrent<br />
(μμA)<br />
Vooltage<br />
(VV)<br />
0.5<br />
50<br />
0<br />
0<br />
-0.5 05<br />
-50 50<br />
-1.0<br />
-100<br />
-1 -1.55<br />
-150<br />
-2.0<br />
-200<br />
-2.5<br />
0 50 100 150<br />
-250 250<br />
200<br />
Time (ns)<br />
Fig Fig. 4 Applied pulse voltage <strong>and</strong> writ<strong>in</strong>g current waveforms of Ta/CoO/Pt for<br />
(a) Set <strong>and</strong> (b) Reset. Set <strong>and</strong> reset conditions are 2.2 V 50 ns <strong>and</strong> -1.4 V 50 ns,<br />
respectively.<br />
2008 IInternational t ti l CConference f on SSolid lid St State t DDevices i <strong>and</strong> d MMaterials t i l (SSDM 2008) 2008).<br />
Date : September 23-26, 2008<br />
RESET current is controlled<br />
by SET operation<br />
(μA)<br />
Current C<br />
Important Issues for <strong>ReRAM</strong> Circuit (TEG) Design<br />
② ③<br />
⑤<br />
④<br />
①<br />
Form<strong>in</strong>g<br />
②⇒③: RESET<br />
④⇒⑤: SET<br />
NVM operation without<br />
Form<strong>in</strong>g process, by<br />
controll<strong>in</strong>g the thicknesses of<br />
the oxide layer y <strong>and</strong> the<br />
metal electrode, <strong>and</strong>/or PTA<br />
The current compliance is<br />
controlled by the transistor<br />
(by a diode <strong>in</strong> the future)<br />
23<br />
24
<strong>Recent</strong> Advance <strong>and</strong> <strong>Prospects</strong> <strong>in</strong><br />
<strong>ReRAM</strong> <strong>Technology</strong><br />
Structure<br />
1. Brief Introduction of <strong>ReRAM</strong><br />
22. The mechanism of <strong>ReRAM</strong> operation<br />
3. <strong>Recent</strong> Advance <strong>in</strong> <strong>ReRAM</strong> technologies<br />
4. Difficult Challenges <strong>and</strong> <strong>Prospects</strong><br />
SRC/NSF/A*STAR Forum on 2020 Semiconductor Memory Strategies: Processes, Devices, <strong>and</strong> Architectures,<br />
Hiro AKINAGA <strong>and</strong> Hisashi SHIMA, Oct. 20-21, 2009, S<strong>in</strong>gapore<br />
An example of importance to control the <strong>in</strong>terface<br />
Coounts<br />
25<br />
20<br />
15<br />
10<br />
5<br />
As prepared<br />
Form<strong>in</strong>g voltage VF Pt/CoO(10nm)/PtTE<br />
n = 24<br />
20 x 20 um 2<br />
After<br />
EB蒸着 <strong>in</strong>terface PtTEcontrol<br />
TE drive<br />
Before スパッタ PtTE<br />
<strong>in</strong>terface (ULVAC) control<br />
0<br />
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0<br />
V F (V)<br />
Form<strong>in</strong>g (1st SET) voltage <strong>and</strong> current (not shown)<br />
are stabilized by the <strong>in</strong>terface control<br />
25<br />
26
TSSC<br />
(pA)<br />
MRS 2010 Fall Meet<strong>in</strong>g Symposium K (K8.20)<br />
TE deposition process dependence of TSC<br />
2 2<br />
10 2<br />
10 2<br />
10 1<br />
10 0<br />
10 -1<br />
10 -2<br />
10 2<br />
(a) SPT-RRAM<br />
TSSC<br />
(pA)<br />
10 1<br />
10 0<br />
10 -1<br />
10 -2<br />
10 2<br />
(b) EB-RRAM<br />
50 100 150 200 250 50 100 150 200 250<br />
T (K)<br />
T (K)<br />
Temperature p ( (T) ) dependence p of TSC ( (thermally y stimulated<br />
current) <strong>in</strong> (a) SPT-RRAM <strong>and</strong> (b) EB-RRAM devices. On the T Tm (K) E ( (eV) V)<br />
whole, the T dependence of TSC <strong>in</strong> SPT-RRAM is gentle over<br />
a wide temperature range. Three dist<strong>in</strong>guish<strong>in</strong>g peaks <strong>in</strong> TSC A 112 0.20<br />
were confirmed for EB EB-RRAM RRAM as depicted by the blue arrows arrows.<br />
This <strong>in</strong>dicates the existence of tightly distributed energy levels<br />
B 165 00.32 32<br />
<strong>in</strong> EB-RRAM.<br />
4<br />
E = kBTm<br />
ln( Tm<br />
/ β )<br />
C 220 0.44<br />
* M.G. Buehler, Solid State Electron. 15, (1972) 69<br />
*<br />
kB: Boltzmann constant<br />
β: Temperature ramp<strong>in</strong>g rate(0.15K/sec)<br />
Form<strong>in</strong>g process <strong>in</strong> RVS test<br />
I-t curve <strong>in</strong> CVS test<br />
t tBD di distribution t ib ti <strong>in</strong> i CVS test t t<br />
T dependence of TSC<br />
A<br />
MRS 2010 Fall Meet<strong>in</strong>g Symposium K (K8.20)<br />
B<br />
EB EB-RRAM RRAM SPT SPT-RRAM RRAM<br />
Smaller VF <strong>and</strong> IF Larger VF <strong>and</strong> IF distributions distributions<br />
Spiky noise observed A monotonic change<br />
Smaller especially p y<br />
for small VCVS LLarger<br />
Peaks observed A monotonic change<br />
EB-RRAM SPT-RRAM The trap levels which dom<strong>in</strong>ate the<br />
Carrier Carrier<br />
current condition dur<strong>in</strong>g the form<strong>in</strong>g<br />
(breakdown) process are affected by<br />
the TE deposition process. In EB-RRAM,<br />
more tightly distributed trap levels exists<br />
<strong>in</strong> the device homogeneously. g y On the<br />
other h<strong>and</strong>s, trap levels <strong>in</strong>duced by the<br />
TE deposition process <strong>in</strong>creases the<br />
r<strong>and</strong>omness of the breakdown process.<br />
C<br />
27<br />
28
<strong>Recent</strong> Advance <strong>and</strong> <strong>Prospects</strong> <strong>in</strong><br />
<strong>ReRAM</strong> <strong>Technology</strong><br />
Structure<br />
1. Brief Introduction of <strong>ReRAM</strong><br />
22. The mechanism of <strong>ReRAM</strong> operation<br />
3. <strong>Recent</strong> Advance <strong>in</strong> <strong>ReRAM</strong> technologies<br />
4. Difficult Challenges <strong>and</strong> <strong>Prospects</strong><br />
currennt<br />
Operat<strong>in</strong>g<br />
Operat<strong>in</strong>g current <strong>and</strong> speed <strong>in</strong> <strong>ReRAM</strong><br />
10mA<br />
1mA<br />
100μA μ<br />
10μA<br />
H. Y. Lee et al.,<br />
ITRI<br />
< 25 μAA IEDM2008<br />
K. Tsunoda<br />
et a al.,Fujitsu , uj tsu<br />
IEDM2007<br />
Z. Wei et al.,<br />
Panasonic,<br />
IEDM2008<br />
Y. Hosoi et al., ,<br />
SHARP&AIST,<br />
IEDM2006<br />
High speed<br />
operation<br />
LLow current t operation ti<br />
YY. Tamai et al al.,<br />
SHARP & AIST<br />
SSDM2008<br />
S. E. Ahn et al.,<br />
Samsung,<br />
Adv. Mater 2008<br />
I. G. Baek et al.,<br />
Samsung,<br />
IEDM2004<br />
1ns 10ns 100ns 1μs μ 10μs μ<br />
Operat<strong>in</strong>g speed<br />
29<br />
30
I. G. Baek et al.,<br />
Samsung,<br />
IEDM2004<br />
Cyccle<br />
enduurance<br />
Current C ( μA)<br />
10 10<br />
10 3<br />
10 2<br />
10 1<br />
Comparison with MOSFET drive current<br />
Y. Hosoi et al.,<br />
SHARP&AIST<br />
SHARP&AIST,<br />
IEDM2006<br />
Z. Wei et al.,<br />
Panasonic, a aso c,<br />
IEDM2008<br />
K. Tsunoda<br />
et al.,Fujitsu<br />
IEDM2007<br />
NMOS ddrive i current t<br />
(ITRS2007, Low operat<strong>in</strong>g power technology)<br />
for gate width of 100 nm<br />
Planar bulk<br />
UTB FD<br />
These NMOS drive current<br />
DG<br />
was calculated for the gate<br />
width of 100 nm.<br />
Y. Tamai et al.,<br />
SHARP & AIST<br />
SSDM2008<br />
S. E. Ahn et al.,<br />
Samsung,<br />
Adv. Mater 2008<br />
H. Y. Lee et al.,<br />
ITRI<br />
IEDM2008<br />
Operat<strong>in</strong>g current of <strong>ReRAM</strong><br />
can be lower than the MOSFET<br />
drive current, <strong>in</strong>dicat<strong>in</strong>g that<br />
<strong>ReRAM</strong> is appropriate ffor<br />
the<br />
low operat<strong>in</strong>g power technology.<br />
2002 2004 2006 2008 2010 2012 2014 2016<br />
Calendar year<br />
:Pt free devices<br />
Cycle y endurance ( (CE) )<br />
10 11<br />
10 12<br />
10<br />
H. Y. Lee et al.,<br />
IEDM2010<br />
Estimation on<br />
required cycle endurance:<br />
11 Z. Wei et al.,<br />
IEDM2010<br />
Technical program<br />
required cycle endurance:<br />
IEDM2008(Pt/Ta2O5/Pt)<br />
(19.7), HfOx-RRAM<br />
10 9<br />
10 8<br />
10 7<br />
10 6<br />
10<br />
10 5<br />
HH. YY. LLee et t al, l IEDM2008<br />
(TiN/HfOx/Ti/TiN)<br />
Samsung<br />
ITRI<br />
C. Yoshida et al,<br />
APL2007(Pt/TiOx/TiN)<br />
Fujitsu<br />
I. G. Baek et al.,<br />
IEDM2004(Pt/NiO/Pt)<br />
Panasonic<br />
ITRI<br />
NEC<br />
H. Y. Lee et al, JJAP<br />
(TiN/HfO (TiN/HfOx/Ti/TiN) /Ti/TiN)<br />
M. Terai et al,IEDM2009<br />
(BE/TiOx/Ta2O5/Pt) ITRI<br />
ITRI<br />
H. Y. Lee et al, JJAP<br />
(TiN/HfOx/Ta)<br />
• Writ<strong>in</strong>g frequency: 1Hz<br />
(1 time / 1 sec)<br />
• A period of use: 1 yrs<br />
31<br />
= 3.1 x 10 7 sec<br />
A practical CE for 1 memory<br />
element is <strong>in</strong> the order of<br />
10 7 times.<br />
CE <strong>in</strong> RRAM exceeds<br />
current Flash memories<br />
National Ts<strong>in</strong>-Hua University<br />
10 4 y<br />
Y. H. Zheng, et al,<br />
CE for s<strong>in</strong>gle bit<br />
IEDM2009 (Si/SiO2/TiON/TiN/W)<br />
Flash memory<br />
10 3<br />
2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014<br />
Calendar Year<br />
CE for multi multi-bit bit<br />
Flash memory<br />
32
Pt<br />
Ti<br />
HfO x<br />
Nanoscale characterization of oxides<br />
Integrated EEELS<br />
signal<br />
30000<br />
25000<br />
20000<br />
15000<br />
10000<br />
5000<br />
BE (a) TE (b)<br />
Pt(BE)/HfO x /Ti(5nm)/Pt<br />
Ti-L (PDA)<br />
O-K (PDA)<br />
O-K (PDA)<br />
Ti-L (PDA)<br />
0<br />
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16<br />
Relative position<br />
Pt<br />
•Electron energy loss spectroscopy (EELS) is a powerful<br />
tool to characterize oxides with a nanoscale resolution.<br />
However, , especially p y for the high-k g oxide such as HfOx, ,<br />
the characterization of Hf edge becomes difficult<br />
HADEF-STEM image of HfOx/Ti <strong>in</strong>terface because of the severe signal <strong>in</strong>tensity decay.<br />
Development of nanoscale metrology for RRAM is<br />
crucial <strong>in</strong> order to improve the operat<strong>in</strong>g reliability of<br />
RRAM <strong>in</strong> association with the material characteristics.<br />
Possible Role-shar<strong>in</strong>g of <strong>ReRAM</strong><br />
CPU<br />
~ 1ns<br />
Cache<br />
~5ns<br />
DRAM ~<br />
10ns<br />
NAND (SSD)<br />
HDD<br />
<strong>ReRAM</strong><br />
(1) Non-volatile<br />
(2) ( ) Byte y Access<br />
(3) Fast operation (~10ns)<br />
1st Target:<br />
To solve I/O bottleneck<br />
33<br />
34
<strong>Recent</strong> Advance <strong>and</strong> <strong>Prospects</strong> <strong>in</strong><br />
<strong>ReRAM</strong> <strong>Technology</strong><br />
2 nd Message from Ak<strong>in</strong>aga<br />
<strong>ReRAM</strong> technology is very young (< 10 years), but<br />
Many y similarities between High-k g <strong>and</strong> <strong>ReRAM</strong> technologies g<br />
We need…<br />
1. Knowledge of Solid State Chemistry <strong>in</strong> Semicond. Tech.<br />
22. Further advance metrology for nano-scale devices<br />
3. Conversation with researchers of emerg<strong>in</strong>g architecture<br />
35<br />
36
cherry on the cake…..<br />
St<strong>and</strong>ard Semiconductor <strong>Technology</strong><br />
carrier dop<strong>in</strong>g<br />
37<br />
38
Mott Transition FET(Mott ( Transistor) )<br />
carrier dop<strong>in</strong>g<br />
(fill<strong>in</strong>g control)<br />
MMott ttI Insulator l t Mtl Metal<br />
·A large number of electrons are Localized electrons become<br />
localized due to electron correlation correlation. it<strong>in</strong>erant by carrier dop<strong>in</strong>g. dop<strong>in</strong>g<br />
Sh Schematics ti of felectric l ti double d blllayer ttransistor it (EDLT)<br />
Source<br />
~1nm EDL<br />
anion (BF (BF4) )<br />
+ + + +<br />
NSNO Channel<br />
Dra<strong>in</strong><br />
Size of the channel 10 μmØ 100 μm<br />
Ionic Liquid: DEME-BF 4<br />
Ionic Liquid<br />
(Electrolyte)<br />
cation<br />
(DEME)<br />
separator p Au/Pt Gate<br />
NdGaO 3<br />
10 10μF/cm F/ 2@10 3H 2@10-3Hz →1.5 × 1014 hole/cm2@VG=-2.5 39<br />
40
NdNiO 3 Channel<br />
-2.5 0 Vgs (V)<br />
Acknowledgement: M. Kawasaki <strong>and</strong> Y. Iwasa<br />
Nonvolatile Diode Switch<br />
Substrate<br />
PtTE<br />
TiO x<br />
PtBE<br />
Fig.1 Schematic Illustration of the Pt/TiO x/Pt Diode.<br />
<strong>Recent</strong>ly, an novel nonvolatile switch<br />
behavior has been successfully<br />
demonstrated <strong>in</strong> a simple s<strong>and</strong>wich<br />
Pt/TiOx/Pt (Fig.1) structure by our group.<br />
After apply<strong>in</strong>g a negative pulse voltage, the<br />
forward current was observed <strong>in</strong> the<br />
negative bias (Fig (Fig.2). 2) It demonstrates that<br />
the diode polarity was switched. The<br />
reproducible switch behavior was<br />
successfully demonstrated (Fig.3).<br />
H. Shima, N. Zhong, H. Ak<strong>in</strong>aga, Appl. Phys. Lett. 94, 082905 (2009).<br />
N. Zhong, H. Shima, H. Ak<strong>in</strong>aga, Jpn. J. Appl. Phys 48, 05DF03 (2009).<br />
Asanuma et al., APL 97, 142110 (2010).<br />
(a)<br />
(b)<br />
Fig. 2 Current-voltage (I-V ) curves of Pt/TiOx/Pt (a)<strong>in</strong>itial state (b) after apply<strong>in</strong>g voltage pulse pulse.<br />
(a) (b)<br />
Fig.3 Current-voltage curves of Pt/TiO x/Pt follow<strong>in</strong>g the<br />
voltage pulse application of (a) h/w=-6.0V/900ms <strong>and</strong> (b)<br />
h/w=+6.0V/900ms.<br />
41<br />
42
Mechanism of the nonvolatile diode switch<br />
(a)<br />
(b)<br />
PtTE<br />
V VO V VO TiO x<br />
V VO V VO VO VO VO PtBE<br />
V O<br />
φ b<br />
w<br />
Pt TiO x (high ( g<br />
x)<br />
+ -<br />
(c) ( w<br />
(c) )<br />
φb Pt TiOx (low<br />
x)<br />
- +<br />
Fig. 4 (a) Profile of VO <strong>in</strong> virg<strong>in</strong> Pt/TiOx/Pt; b<strong>and</strong> structure<br />
<strong>and</strong> equivalent circuit of TiOx/Pt <strong>in</strong>terface [TiOx: (b)<br />
stoichiometriclike <strong>and</strong> (c) heavily reduced] reduced].<br />
(a)<br />
PtTE<br />
V O<br />
V O<br />
TiO x<br />
VO VO VO VO VO PtBE<br />
(b)<br />
PtTE<br />
VO VO VO VO VO TiO x<br />
V O<br />
V O<br />
PtBE<br />
Fig. 5 Profile of V O <strong>in</strong> Pt/TiO x/Pt <strong>and</strong> equivalent circuit of<br />
TiO x/Pt <strong>in</strong>terface TiO x. (a) <strong>in</strong>itial state or after apply<strong>in</strong>g positive<br />
pulse voltage; (b) after apply<strong>in</strong>g negative pulse voltage.<br />
As shown <strong>in</strong> Fig.4, it is assumed that an <strong>in</strong>tr<strong>in</strong>sic-dead layer is produced at the beg<strong>in</strong>n<strong>in</strong>g of<br />
the deposition process<strong>in</strong>g, which contributes to the Ohmic contact of BE/TiO x, due to a good<br />
many of the defects <strong>in</strong> this <strong>in</strong>tr<strong>in</strong>sic-dead layer. For TiO x/TE <strong>in</strong>terface, the <strong>in</strong>terface state is<br />
controlled by the deposition condition. High O2 partial pressure results <strong>in</strong> low concentration of<br />
the defects <strong>in</strong> TiOx layer, therefore, a Schottky barrier would be obta<strong>in</strong>ed.<br />
As shown <strong>in</strong> Fig. 5, the nonvolatile switch<strong>in</strong>g is proposed to be orig<strong>in</strong>ated from the electrical<br />
control of the chemical state <strong>in</strong> TiO TiOx such as the oxygen vacancy concentration at the<br />
<strong>in</strong>terfaces between the TiO x layer <strong>and</strong> Pt electrodes. H. Shima, N. Zhong, H. Ak<strong>in</strong>aga, Appl. Phys. Lett. 94, 082905 (2009).<br />
N. Zhong, H. Shima, H. Ak<strong>in</strong>aga, Appl. Phys. Lett. 96, 042107 (2010).<br />
43<br />
44