Lab 3: Getting Started with DRC, LVS, PEX

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If you see a cross symbol in the report file(Figure 2), which means that this LVS failed. The errors are listed below that cross symbol, you should look at them and correct your layout . Figure 2: Incorrect LVS There are two errors you may have here - we use these errors to show you how to correct the LVS.
(1) In the schematic you designed in lab 1, we are using W =5 and L = 2, while in lab2 when you create the layout, we are using W=4 and L=2. Therefore, you need to change the transistor in the schematic that you created in lab 1 to W=4. To do this, after you open the schematic in Design Architecture, select the transistor, right click the mouse, select "Properties". You will see all the parameters related to the transistor. Select "Width = 5", click OK. and you will be asked to modify the property. Change the Value to 4. (2) Connect the "Bulk" terminal (the arrow terminal) of PMOS to VDD, and connect the Bulk terminal of NMOS to GND. (3) After you modifed the schematic, Check & Save and go to regenerate the design viewpoint. Type the following command in the Console. adk_dve /home/vlsi/cad2008/cadxx/my_inverter/my_inverter/my_inverter Exit and reopen IC station. Run LVS again, and check Report->LVS again, you should see a smiley face, which means your layout is correct now, otherwise repeat previous steps until you see the smiley. You may use cross probing and highlighting (activate the layout window choose Connectivity>Net>Highlight) to understand the relation between the layout and the schematic. When you select the net VSS in the schematic window, you may find that the polygon of P-well in the layout window is not highlighted, while the whole substrate is highlighted. This is because the p-well layer is not defined in the design rules. Figure 3: Correct Lvs
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Lab 3: Getting Started with DRC, LVS, PEX

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