Lab 3: Getting Started with DRC, LVS, PEX

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6) Select the pull-down menu MGC>Setup... to set sessions shown as left right tiling. Click OK. 7) Open the transcript window by selecting MGC>Transcript>Show Transcript. 8) Activate the layout window by clicking on the layout screen and click on the [Check] item on the IC Rules palette and press OK in the Check DRC box that pops up in the lower left corner of the layout window. You will see all the checking results shown in the transcript window. Figure 1: Design Rules Check Window 9) If you got design rules violations, scan these violations by selecting Set Scan to [First], which is located on the palette window (which is only shown when the layout window is active) to see the first error, which is higlighted in the layout. It can be convenient to zoom in on the error to be able to correct it. Press [Next] until all errors are corrected.
At the bottom of the transcript a line such as (DRC compleated, Total Rule Checks:79; Total Results: 0: Total Original Geometries: 41 ... etc). The number beside Total Results signifies design Errors. There may be errors in this lab regarding VDD and GND connection. To solve this, you need to fully cover the VDD and GND with a Metal1 layer. Refer to Lab 2 for details on how to define this layer. Other common errors come from the space limitation violation. A) To edit your cell select the pull down menu File>Cell>Reserve. B) Correct the violations using layout editing techniques learned in Lab 2. C) DRC again (by repeating steps 8-9 above) until no violation is found,. D) Save your cell. File>Cell>Save Cell>Current Context. LVS using ICtrace (M): There exist two types of layout versus schematic (LVS) verifications, Direct and Mask. LVS compares the schematic connections you created in Design Architect to the net connections made in the IC Station. Direct mode compares the electrical connectivity at the current heiarchy and stores the connectivity information directly within the cell. This mode allows for top down design where subcomponents may not be implemented yet. Direct mode views subcomponents from a "Black Box" perspective. Mask mode compares electrical connectivity of the entire ICgraph hierarchical layout with the connectivity of the source circuit. Mask mode is the most complete connectivity checking but on large designs it requires excessive time to extract at every heirarchy. 1) If the active palette is still the ICrules palette, select Back to go back to IC Palette. Then select ICtrace (M) item. 2) Select Logic>Open: from the ICtrace (M) palette and navigate to your /home/vlsi/cad2008/cadxx/my_inverter/my_inverter/lvs directory. Click OK This will open the schematic design viewpoint you created in Design Architect, lab 1. You can visually compare connections between the schematic and the layout, by selecting nets (interconnections) or instances (parts) in the schematic window. If the design does not open; choose File>logic>close and try again. 3) Activate the layout window. Select the pull down menu File>logic>close to allow LVS to perform. 4) Click on LVS in the ICtrace (M) palette. In the dialog box, it will automatically show the Report name as lvs.rep (if it doesn't automatically show, you need to input this). Select Source name with /home/vlsi/cad2008/cadxx/my_inverter/my_inverter/lvs (design viewpoint file you created). Click OK. A) Click on the Setup LVS... button. In the Setup LVS window: change the following items Ground Names: VSS GND Recognize Gates : Yes and click OK. B) Run LVS by pressing [OK] in the LVS (Mask) dialog box. 5) When the LVS check completes, select Report>LVS from ICtrace (M) palette.(Activate layout window to see the ICtrace (M) palette)
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Lab 3: Getting Started with DRC, LVS, PEX

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