Lab 3: Getting Started with DRC, LVS, PEX

Lab 3: Getting Started with DRC, LVS,
Last Modified Jan. 12, 2008
PEX
INTRODUCTION: This lab exercise introduces how to verify the layout of
my_inverter created in the last lab, using Mentor IC verification toolsets. This lab will
cover:
Design rules checking (DRC) with ICrules.
Layout versus schematic (LVS) with ICtrace.
Parasitic extraction (PEX) with ICextract.
DRC with ICrules:All the other IC verification toolsets are integrated within
ICStation environment. ICrules is used for design rules checking (DRC).
1) Generate Design viewpoint: in the Console window, type the following command to
generate design viewpoint:
adk_dve /home/vlsi/cad2008/cadxx/my_inverter/my_inverter
This will generate the design viewpoint. The design viewpoint are used by different
applications, for example, LVS view point. Although the different application's object is
the same one created from Design Architect, their requested information is different
between each other. These applications deal with the design object with different
viewpoints. Just like a person, who is a teacher to his students, a father to his daughter
and a son to his parents. We need to create different viewpoints for different applications.
After back annotation, the design object will include the information from different
viewpoints.
2) start the IC Station by input :
adk_ic &
3) Open the MY_INV cell that you created in lab2 from
/home/vlsi/cad2008/cadxx/physical_lib directory.
4) Set your working directory by using the pull down menu, MGC>Location Map>Set
Working Directory and enter: /home/vlsi/cad2008/cadxx/physical_lib
5) Click on the ICrules item on the IC palette. You may have a look at which design
rules will be checked, by selecting List>Checks. All the rules displayed in the dialog box
are defined in the design rules file $ADK/technology/ic/process/ami05.rules. Select the
rule you want to check and click OK. Click Cancel to close the window.

6) Select the pull-down menu MGC>Setup... to set sessions shown as left right tiling.
Click OK.
7) Open the transcript window by selecting MGC>Transcript>Show Transcript.
8) Activate the layout window by clicking on the layout screen and click on the [Check]
item on the IC Rules palette and press OK in the Check DRC box that pops up in the
lower left corner of the layout window. You will see all the checking results shown in the
transcript window.
Figure 1: Design Rules Check Window
9) If you got design rules violations, scan these violations by selecting Set Scan to
[First], which is located on the palette window (which is only shown when the layout
window is active) to see the first error, which is higlighted in the layout. It can be
convenient to zoom in on the error to be able to correct it. Press [Next] until all errors are
corrected.

At the bottom of the transcript a line such as (DRC compleated, Total Rule Checks:79;
Total Results: 0: Total Original Geometries: 41 ... etc). The number beside Total Results
signifies design Errors.
There may be errors in this lab regarding VDD and GND connection. To solve this, you
need to fully cover the VDD and GND with a Metal1 layer. Refer to Lab 2 for details on
how to define this layer.
Other common errors come from the space limitation violation.
A) To edit your cell select the pull down menu File>Cell>Reserve.
B) Correct the violations using layout editing techniques learned in Lab 2.
C) DRC again (by repeating steps 8-9 above) until no violation is found,.
D) Save your cell. File>Cell>Save Cell>Current Context.
LVS using ICtrace (M): There exist two types of layout versus schematic
(LVS) verifications, Direct and Mask. LVS compares the schematic connections you
created in Design Architect to the net connections made in the IC Station.
Direct mode compares the electrical connectivity at the current heiarchy and stores
the connectivity information directly within the cell. This mode allows for top down
design where subcomponents may not be implemented yet. Direct mode views
subcomponents from a "Black Box" perspective.
Mask mode compares electrical connectivity of the entire ICgraph hierarchical
layout with the connectivity of the source circuit. Mask mode is the most complete
connectivity checking but on large designs it requires excessive time to extract at every
heirarchy.
1) If the active palette is still the ICrules palette, select Back to go back to IC
Palette. Then select ICtrace (M) item.
2) Select Logic>Open: from the ICtrace (M) palette and navigate to your
/home/vlsi/cad2008/cadxx/my_inverter/my_inverter/lvs directory. Click OK
This will open the schematic design viewpoint you created in Design Architect, lab 1.
You can visually compare connections between the schematic and the layout, by selecting
nets (interconnections) or instances (parts) in the schematic window. If the design does
not open; choose File>logic>close and try again.
3) Activate the layout window. Select the pull down menu File>logic>close to allow
LVS to perform.
4) Click on LVS in the ICtrace (M) palette. In the dialog box, it will automatically
show the Report name as lvs.rep (if it doesn't automatically show, you need to input
this). Select Source name with
/home/vlsi/cad2008/cadxx/my_inverter/my_inverter/lvs (design viewpoint file you
created). Click OK.
A) Click on the Setup LVS... button. In the Setup LVS window: change the
following items Ground Names: VSS GND Recognize Gates : Yes and click OK.
B) Run LVS by pressing [OK] in the LVS (Mask) dialog box.
5) When the LVS check completes, select Report>LVS from ICtrace (M)
palette.(Activate layout window to see the ICtrace (M) palette)

If you see a cross symbol in the report file(Figure 2), which means that this LVS failed.
The errors are listed below that cross symbol, you should look at them and correct your
layout .
Figure 2: Incorrect LVS
There are two errors you may have here - we use these errors to show you how to correct
the LVS.

(1) In the schematic you designed in lab 1, we are using W =5 and L = 2, while in
lab2 when you create the layout, we are using W=4 and L=2. Therefore, you need
to change the transistor in the schematic that you created in lab 1 to W=4. To do
this, after you open the schematic in Design Architecture, select the transistor, right
click the mouse, select "Properties". You will see all the parameters related to the
transistor. Select "Width = 5", click OK. and you will be asked to modify the
property. Change the Value to 4.
(2) Connect the "Bulk" terminal (the arrow terminal) of PMOS to VDD, and
connect the Bulk terminal of NMOS to GND.
(3) After you modifed the schematic, Check & Save and go to regenerate the
design viewpoint. Type the following command in the Console.
adk_dve /home/vlsi/cad2008/cadxx/my_inverter/my_inverter/my_inverter
Exit and reopen IC station. Run LVS again, and check Report->LVS again, you should
see a smiley face, which means your layout is correct now, otherwise repeat previous
steps until you see the smiley.
You may use cross probing and highlighting (activate the layout window choose
Connectivity>Net>Highlight) to understand the relation between the layout and the
schematic. When you select the net VSS in the schematic window, you may find that the
polygon of P-well in the layout window is not highlighted, while the whole substrate is
highlighted. This is because the p-well layer is not defined in the design rules.
Figure 3: Correct Lvs

Post-layout Extraction using Calibre PEX:
With the layout complete and passing LVS and DRC, it is time to extract the layout
parasitic netlist. This will give you a spice netlist of your layout complete with resistance,
parasitic capacitance and coupling capacitance. For the extraction process you will use
Calibre Interactive - PEX.
Before you run PEX, you need to generate the netlist. Got to ICTrace (M) from the IC
Palettes, click on [Netlist]. In the pop-up window, input a name for the netlist :
MY_INV_netlist, keep all the other setting as default and click OK This will generate
netlist for your PEX.
Step 1: In IC Stations menu bar, select Calibre -> Run PEX. In the pop-up window,
input the Path to Calibre tree
$CAL_HOME
This will launch Calibre Interactive - PEX.

Step 2: If this is your first time running Calibre Interactive - PEX you will need to
create a new runset so just click Cancel. If you have run Calibre before find the previous
runset. This will simplify setting up Calibre.
Step 3: Begin by clicking the Rules button and setting the rule file and working
directory. The rule file should be of the form:
$ADK/technology/ic/process/ami05.calibre.rules
The Rules button should now be green.
Step 4: Next click the Inputs button. The Layout tab should already be set correctly.
Under the H-Cells tab, change the PEX x-cell file path to
$ADK/technology/adk.hcell.
Under "Netlist" tab, change the "Files" to be "MY_INV_netlist" that you generated.
Step 5: Now select the Outputs button. At the top, the Extraction Type should be
Transistor Level and you can choose one of the following types:
RCC - Distributed RC network with coupling capacitors
RC - Distributed RC network without coupling capacitors
C - Lumped net capacitance with coupling capacitors
Select the first one: Distributed RC + coupling caps
Step 6: In the Netlist tab you can setup the output format and file name. Choose DSPF as
the Format and Use Names From: LAYOUT. You should also see there is a name for
File: " MY_INV.pex.netlist ". You may change this file name to be
"MY_INV.pex.netlist_DSPF" for you to remember that the output file is a DSPF
format. Remember this output file name since you will need this output file for postlayout
simulation.
Step 7: Next choose Setup -> PEX Options from the menu bar. In the Netlist tab click
the Ground node name: check box and enter GND. In the LVS Options tab set
Recognize gates: to All. Also enter the following:
Power nets: VDD
Ground nets: GND
Step 8: You should now be all set to perform the extraction so click Run PEX. If a pop
up asks to overwrite the layout file click OK to ensure Calibre sees any recent changes to
your layout.
Step 9: When Calibre has completed the extraction a window will pop up showing the
top level of the extracted netlist. Notice that there may be up to two additional netlists
which will be included into the top level. The first will contain the RC networks and the
second will contain the coupling capacitors.
Step 10: Close IC station