gate-all-around silicon nanowires for hybrid single electron ...

Gate-all-around Silicon nanowireS for Hybrid
SinGle electron tranSiStor/cMoS applicationS
THÈSE N O 3983 (2008)
PRÉSENTÉE LE 18 JANVIER 2008
À LA FACULTÉ DES SCIENCES ET TECHNIQUES DE L'INGÉNIEUR
LABORATOIRE D'ÉLECTRONIQUE GÉNÉRALE 2
SECTION DE GÉNIE ÉLECTRIQUE ET ÉLECTRONIQUE
ÉCOLE POLYTECHNIQUE FÉDÉRALE DE LAUSANNE
POUR L'OBTENTION DU GRADE DE DOCTEUR ÈS SCIENCES
PAR
Vincent POTT
ingénieur en microtechnique diplômé EPF
de nationalité suisse et originaire de Mollens (VS)
acceptée sur proposition du jury:
Prof. J. R. Mosig, président du jury
Prof. M. A. Ionescu, directeur de thèse
Prof. G. De Micheli, rapporteur
Prof. S. Mantl, rapporteur
Dr M.-N. Séméria, rapporteur
Lausanne, EPFL
2007

REMERCIEMENTS
Un travail de thèse représente un effort d’équipe. Un dispositif intégré avec succès, un
doute levé ou une analyse pertinente, tout cela fait partie de la synthèse demandée à un
doctorant et résumée dans ce manuscrit. Les résultats présentés n’auraient pas été
possibles sans le soutien de mes collègues, de mes amis et de ma famille.
Je tiens en premier à adresser mes remerciements les plus sincères à mon directeur de
thèse, le Prof. Adrian M. Ionescu, pour son support, ses encouragements et son
enthousiasme. C’est avec lui que j’ai eu la chance de découvrir le monde de la recherche
scientifique.
Je souhaite aussi adresser ma reconnaissance aux membres du jury de thèse, et en
premier à son président, le Prof. Juan Mosig. Je souhaite aussi souligner les remarques
pertinentes des rapporteurs, qui ont permis d’améliorer la consistance de ce travail. Ma
gratitude s’adresse au Dr Marie-Noëlle Séméria du CEA-Grenoble, au Prof. Siegfried
Mantl du Forschungszentrum-Jülich et au Prof. Giovanni de Micheli de l’EPFL.
Au sein du laboratoire d’électronique générale, j’ai bénéficié de l’aide du Dr Didier
Bouvet. Je lui dois de précieux conseils, j’ai toujours apprécié son pragmatisme et il m’a
beaucoup appris en microtechnologie. Je souhaite aussi adresser ma gratitude à Kirsten
Moselund pour de nombreuses discussions sur la technologie nano-fil, ainsi que pour sa
gentillesse, sa générosité et sa rigueur scientifique.
Ma reconnaissance s’adresse également à Michaël Pavius du Centre de Micro et
Nanotechnologie de l’EPFL. C’est par sa compétence et sa disponibilité que toutes les
coupes FIB et les lamelles TEM ont été réalisées avec succès. Et au-delà de ses
compétences, je veux aussi lui dire merci pour son amitié. Au Centre de Micro et
Nanotechnologie, j’ai pu également bénéficier du support inconditionnel du Dr Philippe
Flückiger et de toute son équipe.
Dans mon laboratoire, j’ai toujours pu compter sur le support de mes collègues. Je suis
plus particulièrement reconnaissant au Dr Paul Salet pour la relecture du manuscrit de
thèse, ainsi qu’à Dimitrios Tsamados, Marco Mazza et Paolo Dainesi pour leurs
remarques. Je tiens aussi à adresser un clin d’oeil à mon ancien collègue Serge Ecoffey
pour sa collaboration en salle blanche. Je veux enfin remercier Santanu Mahapatra et
Daniel Grogg, pour avoir successivement partagé le bureau ELB240 avec moi.
L’organisation du laboratoire d’électronique générale fut durant ces années excellente. Je
la dois notamment à Joseph Guzzardi pour l’informatique et à Roland Jaques pour les
appareils de caractérisation. Ce laboratoire vit aussi grâce au sourire et à l’efficacité de
ses secrétaires Danièle, Isabelle et Karin. Enfin, merci à Marc Pastre et à Danica
Stefanovic pour leurs conseils de rédaction et de mise-en-page de ce travail.
A l’EPFL, j’ai eu la chance de collaborer avec les groupes du Prof. Jürgen Brugger et du
Prof. Yusuf Leblebici. Je me dois aussi de remercier le Dr Marco Cantoni pour
l’observation d’images TEM et le Dr Pavel Kejik pour le bonding de circuits.
Par nos projets de recherche à l’échelle européenne, j’ai également bénéficié du support
du groupe du Prof. Dieter Kern de l’Université de Tübingen pour des étapes de
technologie, des mesures de microscopie Raman par le Dr Sarah Olsen de l’Université de
Newcastle et de discussions enrichissantes en physique quantique avec le Prof. Jean-
Pierre Colinge de l’Université de Tyndall en Irlande.
Enfin, sans le support de mes amis, cette thèse n’aurait pas été possible. Je citerais
Gonzague, Nicolas, François et Mélanie. Artur, je te dois aussi beaucoup, et en
particulier ta bonne humeur!
Je veux aussi noter les encouragements sans faille de ma famille, et plus spécialement de
ma tante Laurence Ulrich et de mon oncle Jean-Marc Bornet. Pour finir, je souhaiterais
adresser ma reconnaissance à mon frère Julien et à mes parents Anne et Guy, pour
m’avoir guidé et soutenu depuis toujours.

Table of contents 1
TABLE OF CONTENTS
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Fundings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Résumé. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
List of acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 Past, present and future . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2 The EPFL hybrid NANO-CMOS vision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 CMOS scaling and nano-scale CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.1 The MOS transistor: a short overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.2 Short CMOS history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.3 Moore’s law and scaling rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3.4 Nano-scale CMOS: problems and solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4 Tri-dimensional MOSFET structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.1 Silicon-on-insulator (SOI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.2 Double-gate, FinFET and Silicon-on-Nothing . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4.3 The vertical MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.4.4 Tri-Gate, Pi-Gate and Omega-Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.4.5 The silicon nanowire gate-all-around architecture . . . . . . . . . . . . . . . . . . . . . . . . 31
1.4.6 The tunnel FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.4.7 Tri-dimensional devices summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.5 Technology hybridization with emerging devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.5.1 What makes a logic family efficient? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.5.2 The single electron transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.5.3 Multiple-island single electron devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.5.4 Resonant tunneling devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.5.5 Carbon nanotubes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.5.6 1D nanowires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.5.7 Macro-molecular devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.5.8 Spintronics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.5.9 Ferromagnetic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.5.10 Devices comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.5.11 Circuits and systems hybridization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
1.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1.6.1 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1.7 Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chapter 2: Silicon nanowire for MOS/SET combined functionality . . . . . . . 59
2.1 Bridge the gap with the single electron transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.2 The crystalline silicon SET: geometry and architecture . . . . . . . . . . . . . . . . . . . . . . 61
2.2.1 Pattern dependent oxidation of SOI nano-structures . . . . . . . . . . . . . . . . . . . . . . 61
2.2.2 Coulomb Blockade in MOS transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.2.3 Highly doped silicon nanowires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.2.4 Electrically induced SET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.2.5 Gate-all-around silicon nanowires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.2.6 Other silicon SET integration technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3 Silicon nanowire devices comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.4 Finite element analysis of silicon nanowires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.4.1 Corner effect in triangular cross-section devices . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.4.2 Density-Gradient simulation of circular nanowires . . . . . . . . . . . . . . . . . . . . . . . 72
2.5 The SET-NEMS architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2 Table of contents
2.6 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.6.1 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.7 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Chapter 3: Hybrid SET/MOS technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.1 The smaller, the better . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
3.2 Lateral Pattern Definition (LPD) technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
3.2.1 Polysilicon oxidation LPD process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.2.2 Silicon oxidation LPD process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.2.3 Nitride LPD nanowires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.3 Focused ion beam prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.3.1 Introduction to focused ion beam. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.3.2 FIB prototyping examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.3.3 SOI direct milling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.3.4 Resist milling and pattern transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.3.5 Non FIB-cut devices measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.3.6 FIB-cut silicon nanowire measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.7 FIB milling perspectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.4 Gate-all-around nanowires on bulk silicon. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
3.4.1 Device fabrication and morphology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.4.2 TEM observation and cross-section shape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.4.3 The implant and anneal matter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.5 Gate-all-around SOI devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
3.5.1 SOI wire formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.5.2 Gate stack formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.5.3 Rapid thermal annealing qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.6 Process scalability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
3.7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
3.7.1 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.8 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Chapter 4: Characterization and analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.1 The probe setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
4.2 Gate-all-around MOS characterization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
4.2.1 Room temperature characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.2.2 Temperature dependent characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.2.3 Mobility extraction and analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.2.4 Enhanced carrier mobility due to PADOX strain . . . . . . . . . . . . . . . . . . . . . . . 118
4.3 Cryogenic local-SOI devices characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
4.3.1 Coulomb oscillations and Coulomb gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.3.2 Cryogenic measurement analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.3.3 Kink effect in local-SOI devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.4 SOI transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
4.4.1 Room temperature characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.5 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
4.5.1 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.6 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Chapter 5: Conclusion and perspectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.1 Major achievements in this work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
5.2 Perspectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Appendix A: PBL and SOI oxidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Appendix B: List of publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Appendix C: Curriculum Vitae. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Fundings 3
FUNDINGS
This PhD thesis has been jointly funded by:
The Network of Excellence SINANO (Silicon-based Nanodevices).
SINANO is funded by the European Commission under the sixth EU
Framework Programme for Research and Technological Development.
(IST-506844).
and
The Swiss National Science Foundation, Project: Nano-scale hybrid
CMOS-SET IC architectures (NANO-IC).
Independent Basic Research - Number: 200021-101847.

Abstract 5
ABSTRACT
Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The
remarkable success story of Moore's law during the last 40 years, predicting the evolution of
electronic device performances related to miniaturization, has always been respected.
However, electron device challenges are now much more complex. In order to keep Moore's law
living, device scaling-down is not enough. So called material and geometry technology boosters have
been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some
booster examples, used at sub-micron scale.
This work proposes an investigation of a hybrid CMOS/SET technology, based on gate-all-around
silicon nanowires. It is shown that a silicon nanowire can serve two device purposes: first as
innovative 3D metal-oxide-semiconductor field effect transistor (MOSFET), and second as single
electron transistor (SET).
The SET is a solid-state electronic device, which controls the transport of a unique or a few electrons.
SET functions are not limited by its nano-scaled structure. The smaller is the better. SET consists of
a small conductive quantum dot, called island, connected to two reservoirs acting as drain and source
by tunnel junctions. The size of the island should be as small as possible - typical values ranging
from 1 to 4nm - in order to have room temperature operation. Electron transport from source to
island, and from island to drain is controlled by a capacitively coupled gate. The nano-scale size of
the island makes the carrier electrostatic repulsion efficient. This effect is called Coulomb Blockade.
SET advantages are an ultra-reduced size and a very low power consumption, while SET challenges
are variability related to dimension control and background charge effect, room temperature
operation and a reduced fan-out.
The first chapter of this thesis introduces ideas of up-to-date MOS and SET devices and shows how
to combine MOS and SET to obtain original electronic functions. The second chapter is a discussion
of the nanowire as a technology platform for the integration of SET devices and also presents TCAD
simulation results.
Key contributions are reported in chapter three. This is the original and complete description of the
different top-down processes used for the integration of a gate-all-around MOS/SET platform.
Samples integrated at the EPFL Center of Microtechnology (CMI) are presented. Different
approaches have been studied and used in order to overcome lithographic limitations, and to have a
fast and reliable integration at moderate cost. This includes auto-aligned techniques, focused ion
beam prototyping, and top-down local-SOI and true-SOI nanowires.
The local-SOI technique based on silicon nano-channel wires has given the best results and offers a
lot of flexibility in term of wire cross-sections and shapes. Gate-all-around silicon nanowires,
obtained by sacrificial etching and self-limited oxidation, with a circular 5nm diameter cross-section
have been characterized.
Chapter four is the validation by measurements of both SET and MOS devices. Excellent room
temperature characteristics have been observed in MOS structures, while both I D -V G Coulomb
oscillations and I D -V D Coulomb gap are observed on smaller structures at cryogenic temperature
(T

Résumé 7
RÉSUMÉ
La miniaturisation des dispositifs semi-conducteurs s’approche de limites physiques fondamentales.
En effet, la progression constante des composants CMOS, établie depuis plus de 40 ans par la
fameuse loi de Moore, a toujours été respectée, que ce soit en termes de puissance, de rapidité ou de
taille des composants. Ce succès a permis le développement rapide des télécommunications.
Cependant, un tel progrès n’est pas gratuit. Afin de soutenir une telle évolution, la miniaturisation ne
suffit plus, la microélectronique traditionnelle semble à bout de souffle et un changement radical est
inévitable: celui de la technologie post-CMOS.
La loi de Moore est donc à un croisement, et c’est justement à ce croisement que se situe ce travail de
thèse. Les deux voies envisageables sont d’une part celle qui semble la plus prudente et qui consiste
à pousser la technologie CMOS à un optimum. D’autre part, puisque la technologie permet la
fabrication de dispositifs nanométriques, pourquoi ne pas exploiter des principes physiques
prédominants à cette échelle? Cette réflexion nous a conduit à une voie hybride, qui consiste à
réaliser sur un même substrat, à la fois des transistors MOS et des transistors à électron unique (SET:
single electron transistor) à partir d’une plate-forme technologique commune basée sur le nano-fil en
silicium.
Un transistor SET est un composant qui permet le contrôle d’un seul électron à la fois! Sa partie
centrale est un îlot conducteur de dimension nanométrique, contacté à deux réservoirs par des
jonctions tunnel. Le diamètre de l’îlot doit être de 1 à 4nm pour permettre un fonctionnement correct
à température ambiante. A cette échelle, la répulsion électrostatique entre deux électrons permet un
transfert quantifié de charges. Ce principe est appelé blocage de Coulomb. Le transfert d’électrons
est contrôlé par une électrode de grille couplée de manière capacitive. Les avantages du SET sont
une taille minimale et une puissance dissipée réduite au maximum. Par contre, la fabrication de SET
de manière reproductible et à large échelle est un casse-tête technologique toujours irrésolu!
Ce manuscrit de thèse s’articule autour de différents chapitres. Le premier présente l’état de l’art des
technologies actuelles MOS et SET, et justifie le choix d’une intégration hybride. Le second chapitre
introduit le concept de nano-fil en silicium et présente quelques résultats de simulation originaux,
notamment sur les discrétisations d’énergie qui prédominent à échelle nanométrique.
La partie principale de ce travail est décrite dans le troisième chapitre, consacré aux différents
procédés d’intégration étudiés durant ce travail. Sur les quatre procédés évalués, la technique topdown
appelée local-SOI a sans aucun doute donné les meilleurs résultats. Cependant, il nous a paru
intéressant de tous les présenter pour justifier certaines approches. Toutes ces techniques ont été
développées au Centre de Microtechnologie (CMI) de l’EPFL.
La fabrication de nano-fils quantiques par la technique local-SOI est basée sur la gravure et
l’oxydation sacrificielle de structures en silicium. Cette technique est simple, de bon rendement et
peu coûteuse. Différentes longueurs de fils et des sections de forme variable ont été obtenues. Un fil
circulaire de diamètre de 5nm représente la dimension minimale réalisée par ce procédé.
Le quatrième chapitre présente les mesures électriques de nano-fils en silicium, et démontre
comment cette unique structure permet à la fois d’obtenir des caractéristiques de type MOS et de
type SET, selon les dimensions, les longueurs de canal et la température de fonctionnement. Le
blocage de Coulomb, en I D -V G et I D -V D , a été clairement mesuré à une température inférieure à
20K. Les caractéristiques sont excellentes en comparaison de nano-fils de croissance grâce à des
contacts purement ohmiques. La mesure de stress dans le fil par spectroscopie Raman a également
démontré une mobilité de porteurs très élevée (μ n =850cm 2 /Vs). Une étude des résultats basée sur la
simulation par éléments finis complète l’analyse des mesures.
Ce travail de thèse a ainsi prouvé une intégration hybride de transistors MOS et SET. Une telle
réalisation est une solution élégante pour un transfert en douceur du CMOS vers de nouveaux
composants nanoélectroniques.
Mots-clés: Microélectronique, Nanoélectronique, Nanotechnologie, SET, MOS, Silicium, Fil
quantique

List of acronyms 9
LIST OF ACRONYMS
1D-, 2D-, 3D- one-, two-, three-dimensional
AFM atomic force microscopy
ANP solution of acetic, nitric and phosphoric acid
BHF buffered fluorhydric acid
BJT bipolar junction transistor
BOX buried oxide
BSE back scattered electrons
CB Coulomb Blockade
CMI EPFL Center of Micro and Nanotechnology
CMP chemical mechanical planarization
CMOS complementary metal-oxide-semiconductor
CNT carbon nanotube
CPU central processing unit
DG double gate
DIBL drain induced barrier lowering
DOS density of states
DWL direct writing laser
EG electron gas
EOT equivalent oxide thickness
EPFL Ecole Polytechnique Fédérale de Lausanne
FD fully depleted
FET field effect transistor
FIB focused ion beam
FinFET field effect transistor with fin channel
GAA gate all around
HBT heterojunction bipolar transistor
HEMT high electron mobility transistor
HP high performance
HSQ hydrogen silsesquioxane
IC integrated circuit
ICP inductive coupled plasma
ITRS international technology roadmap for semiconductor
LEG laboratoire d’électronique générale
LOP low operating power
LPCVD low pressure chemical vapor deposition
LSI large scale integration
LOCOS local oxidation of silicon
LPD latteral pattern definition
LTO low temperature oxide
MC Monte Carlo
MEMS micro-electro-mechanical systems
MOSFET metal-oxide-semiconductor field effect transistor
MVL multiple value logic
MWCNT multi-walled carbon nanotube
NEMS nano-electro-mechanical systems
NW nanowire
PADOX pattern dependent oxidation

10 List of acronyms
PBL poly-buffered locos
PD partially depleted
PID proportional integral derivative
PMA post metallization anneal
PolySi polycrystalline silicon
PSG phosphosilicate glass
QD quantum dot
QDT quantum dot transistor
R&D research and development
RIE reactive ion etching
RT room temperature
RTA rapid thermal annealing
RTD resonant tunneling device
RTT resonant tunneling transistor
S/D source and drain
SCE short channel effect
SE secondary electrons
SED single electron device
SEM scanning electron microscopy
SET single electron transistor
SG-MOSFET suspended-gate MOSFET
SHT single hole transistor
SIM scanning ion microscopy
SIMOX separation by implantation of oxygen
SIMS secondary ion mass spectrometry
SiNW silicon nanowire
SMT stress memory technique
SNR signal-to-noise ratio
SOI silicon on insulator
SON silicon on nothing
Sslope subthreshold slope
STI shallow trench isolation
STM scanning tunneling microscopy
STN signal to noise
SWCNT single-walled carbon nanotube
TEOS tetra-ethyl-ortho-silicate
TEM transmission electron microscopy
ULSI ultra large scale integration
UTB ultra thin body
VCO voltage-controlled oscillator
VLSI very large scale integration
V-PADOX vertical pattern dependent oxidation
WF work function

Chapter 1
Introduction
This chapter is a general introduction to the thesis work. It gives an overview of current silicon
technology, research, and future trends. Based on Moore’s law of MOS devices scaling, the
continuous evolution of devices performances is presented. CMOS limitations - in terms of physics,
modeling and technology - are also explained; in order to clearly understand what challenges are
now facing semiconductor engineers. Scaling effects, which affect transport characteristics in ultrascaled
devices, are described. Proposed nano-scale CMOS solutions are discussed, like new material
integration and device architecture (3D MOSFET).
Then, non-CMOS emerging devices for logic applications are introduced. Based on the International
Technology Roadmap for Semiconductors (ITRS), an evaluation and a comparison between novel
electron devices is given. The single electron transistor (SET) is considered now as a potential
alternative solution. In terms of power consumption and integration level, the SET has much better
performances than up-to-date MOS devices. The unique hybrid MOS-SET technology and circuit cointegration
possibilities are also demonstrated. Basic physics, functions and operating principles of
MOS and SET are emphasized.
Even if long-term predictability of semiconductor industry seems highly risky, this introduction
chapter clearly motivates this thesis work on hybrid SET/MOS applications.

12 CHAPTER 1: Introduction
1.1 Past, present and future
In this introduction, a summary of past results, current research and future trends in the field of
semiconductor industry is given, and especially in silicon device research for logic applications.
There are many physical effects that can be used to compute information [Was05], but the choice of
electron devices is astonishingly very limited. The MOS transistor has been the successful device for
more than 40 years and will, with no doubt, continue to be a key device. But alternative devices, as
carbon nanotubes or single electron transistors exist, and preliminary results are encouraging. Even if
we are still far away from any ideal device, semiconductor engineers have to find solutions in order
to satisfy the huge need in efficient electronic applications. The list of requirements that devices
should ideally fulfill is long and will be developed further, but we can already mention the device
size, speed, power consumption and reliability as essential characteristics. All classes of devices
have both technology and physics limitations, and this is still too early to say which structure will
give long term best performances.
Gordon E. Moore - Intel’s co-founder and the writer of the famous Moore’s law of exponential
device scaling - said about his law: No exponential is forever, but ’’forever’’ can be delayed [Moo03].
This means that devices can be highly improved. His vision is still remarkably correct, even though
smallest structures have now reached the atomic scale.
The target of this introduction part is to motivate the hybrid MOS/SET approach we choose. Results
obtained and discussed in next chapters are demonstrating that combining MOS devices and single
electron transistors may be a possible approach on the long road to ultimate computing.
Past - a success story
Present - we are at a
crossing point.
TIME TO
MARKET
CMOS
MOORE’S LAW
SCALING
TECHNOLOGY
STOP
NANO-CMOS
EMERGING DEVICES
HYBRIDIZATION
QUANTUM
POWER
SAVING
Future - where shall we go?
Before starting an original scientific research work, authors should
always be focused on previous works and state-of-the-art
contributions. Silicon technology is a more-than-50-year old story,
which includes a long list of outstanding results.
The first part of this introduction includes a description of a basic
MOS device, and gives also a brief history of IC integration. Then
the Moore’s law on scaling is discussed. Difficulties that engineers
are facing now are described. These limitations are not only
resulting from technology, but also from physics itself. Now most
advanced MOS devices have channel lengths shorter than 10nm,
which means only 20 atoms of silicon along the channel.
The semiconductor industry is now living a transition phase. At
nano-size scale, the so-called good design rules are no more valid.
Performance boosters that have been introduced in Si technology are
explained in this introduction. They consist in two main categories.
The first category is based on new materials, like metal gate or
strained silicon. The second one consists in new 3D device
geometries, to which a sub-chapter is dedicated. A particular focus
is done on silicon nanowires. Best device performances are often
obtained by smart combinations of different boosters.
The last sub-chapter of this introduction presents a new class of
devices, called emerging devices by the ITRS. Single electron
transistor, carbon nanotubes or spin-based transistors are some
examples of emerging devices. Those devices have specific
advantages and limitations, but they are all considered as extremely
interesting in post-CMOS ultra-large scale integration.
A more detailed description of the SET is given, because this device
is the one we choose to be co-integrated in a silicon nanowire
technology platform. The last part presents some hybrid applications
based on combined MOS and emerging devices circuitry.

The EPFL hybrid NANO-CMOS vision 13
1.2 The EPFL hybrid NANO-CMOS vision
This thesis is a part of global NANO and CMOS researches developed at the EPFL Electronics
Laboratory (LEG). The main target of this first chapter is a detailed description of such an approach,
with a specific focus on challenges that need to be overcome.
New-nano:
Hybridization
Nanotechnology Microelectronic
Figure 1.1: When nanotechnology meets microelectronics. Nano-CMOS devices (boosted devices
and 3D MOS architecture) and the single electron transistors (SET) are both exploiting potentials
from the nano and the micro sides.
There are many scientifically intriguing examples of new nano-devices, including the single electron
transistor. In order to optimize the compatibility between CMOS and SET, we choose silicon as a
common material platform. The work was also essentially focused on a top-down approach. Our
conception was not to process a few nano-scale devices, but either to propose a complete hybrid
process for large scale integration. This vision is motivated by the strength of nano-scale devices to
do massive parallel operations at low power consumption, impossible to build only upon CMOS.
After many tests, we found that the silicon nanowire built in a gate-all-around geometry is a very
appealing and versatile structure. Figure 1.2 presents how we bridge together science at the micro
and nano scale.
D
innovation
bottom up
low power
consumption
new functions
NANO-CMOS
SET
maturity
moderate cost
standard process
reliability
Nano-devices Nano-technology
Si dot
5nm
Nanotechnology is innovation for tomorrow’s world
2μm
Silicon
S
Top-down
Micro-technology
New nano concepts
and modeling
Figure 1.2: Some original results further developed in this report. These include functional nanodevices,
the use of dedicated nano-technology tools, a top-down micro-technology optimization and
new nano-modeling.
For the rest of this work, we consider the following definition of Nanotechnology: This is the art and
science to organize the matter from the atomic size up to 100nm, to exploit unique physical
properties that predominate at this scale, and to built systems at this size. In this way,
nanotechnology is not only a shrink in size; this is much more... and this report will show why this is
much more!

14 CHAPTER 1: Introduction
1.3 CMOS scaling and nano-scale CMOS
In this sub-chapter, basic ideas, novel materials and new concepts of the silicon MOSFET are
described. The target of this section is not to give a complete modeling of a MOS transistor, but
rather to briefly describe the MOS architecture and to summarize its main limitations and
advantages. There is a considerable literature on MOS devices. Some references are giving a general
overview [Sze02], other are focused on more specific goals; as technology integration [Mad02].
This chapter will also be placed in its historical context. It seems important to have an excellent
knowledge of results that have been obtained during the last decades. A crystal clear view of actual
R&D in semiconductor industry is absolutely mandatory to make any predictions. We are now living
an exciting CMOS evolution, because dimensions are close to the atomic dimensions and scaling
will inevitably decrease or even stop at an optimized scale.
The last part of this sub-chapter is an evaluation of technology boosters that have been introduced in
order to correct non-linear scaling and material limitations. This section is also of great importance
for the next part of this work, because the silicon-based SET technology is almost exclusively
depending on CMOS technology, which is a mature technology and that represents more than 70% of
worldwide IC production. CMOS technology is of course the driver for many new nanotechnologies,
not only SET, but also other silicon-based emerging devices.
1.3.1 The MOS transistor: a short overview
The MOS transistor structure
In this part, we describe the structure and operation modes of a planar bulk MOS transistor with
inversion channel. A MOS transistor is a three-terminal semiconductor structure, as displayed in
Figure 1.3, which is used as electronic switch, amplifier or oscillator in integrated circuits. The free
carrier level in a MOS channel is controlled by the electrostatic effect of the gate-to-channel
capacitance, using the gate oxide as capacitor dielectrics. The channel is connected to two highly
doped regions - n+ doped for NMOS - and the total current flow is a function of the drain-to-source
bias. This device can therefore be considered as a tunable resistor, with current flow in a parallel 2D
surface.
A MOS transistor is a unipolar device, NMOS have electrons as free charge carriers and PMOS
holes. Both types of devices are needed in CMOS technology. CMOS integration is done using
planar technology in clean-room. Materials used are mainly silicon dioxide (SiO 2 ) as gate dielectrics,
highly doped poly-crystalline silicon as gate and metals (Al, Cu) for contacts.
Spacers
n+
Drain metal
contact
Channel
length
Channel
width
Figure 1.3: Structure of a basic n-channel MOS transistor, including gate spacers.
Typical dimensions of a 0.18μm CMOS technology are the following [Sko05]:
• Gate length .......................................................................... L G = 0.18μm
• Channel length .................................................................... L = 0.13μm
• Gate oxide thickness ........................................................... T ox = 4nm
• S/D junction depth............................................................... x j = 0.15μm
• Channel width ..................................................................... W = 0.35μm
• Substrate doping.................................................................. N B = 5x10 17 cm -3
Gate
Gate
oxide
n+
p-type silicon
substrate
Source metal
contact

CMOS scaling and nano-scale CMOS 15
MOS operating modes
Static current modeling in a MOS transistor is usually evaluated with the band structure of the MOS
capacitor gate - gate oxide - silicon. The total charge between the two sides of the MOS capacitor are
equal.
Depending on the gate-to-channel bias, all modes of operation can be given as a function of Ψ S , the
surface potential, and Ψ B , the difference between the Fermi level and the intrinsic level in silicon.
Table 1.1 summarizes all operating modes and will serve as a reference for the next chapters.
TABLE 1.1: OPERATING MODES OF A NMOS DEVICE, FROM ACCUMULATION TO STRONG INVERSION.
Table 1.1 has the advantage to describe an operation principle that is not dependent from any
dimensions or particular structure of the device. The total current through the transistor I D is
computed as a function of the surface potential as well as S/D and bulk bias conditions.
An advanced MOS example
Surface potential Operating mode
ψS < 0
ψ S
=
0
0 < ψS < ψB ψ S
=
ψ B
ψB > ψS > 2ψB ψ S
=
2ψ B
ψS >
2ψB Accumulation of holes
Flat-band condition
Depletion of holes
Midgap with intrinsic concentration
Weak inversion regime
Threshold voltage condition
Strong inversion regime
In comparison with 1970s devices, architectures and dimensions of actual MOS transistors are
completely different. However, operating modes are strictly equivalent. The example presented in
Figure 1.4 is a multi-bridge device with a 240nm channel length published in 2004 [Lee04a]. A
performance comparison is made between this device and a planar FET. Strong improvements are
revealed in terms of a steeper sub-threshold slope and a higher ON-current.
Figure 1.4: SEM channel cross-section picture of an advanced MOSFET transistor (left). This
device is composed by two epitaxial silicon multi-bridge channels and a gate-all-around structure.
The channel length is 240nm. I D -V G characteristics of the same device with a planar FET
comparison are depicted (right) [Lee04a].
The different architectures of MOS devices with improved performances and architectures will be
described in the next part of this introduction chapter.

16 CHAPTER 1: Introduction
1.3.2 Short CMOS history
Semiconductor materials have been used in the electronics industry before the invention of the first
transistor. At the beginning of the 20 th century, a device called cat’s whisker was used as radio
detector. This device was made of a tungsten filament moving over a surface of silicon carbide. This
device was then replaced by first vacuum tubes, invented by Lee de Forest in 1906, and research on
semiconductor devices was for a while put to one side. However, vacuum tubes were consuming a lot
of power and had a poor reliability.
During World War II, tube-based radio was not efficient enough and semiconductor devices have
focused again a lot of interest. Russell Ohl, of Bell Labs (New Jersey), has decided to improve the
concept of cat’s whisker, and together with Walter Brattain he observed the first pn junction effect in
a doped semiconductor device. These developments continued after the War. The group of William
Shockley worked on the realization of the first triode-like semiconductor device. First results have
been obtained by Ohl and Brattain, even a lack of repeatability in measurements. At the same time
was developed the quantum surface physics to account for the electronic behavior of devices.
The first operational transistor was finally invented in 1947 by Bardeen, Shockley and Brattain
(Figure 1.5). This device was a PNP point-contact germanium transistor and was used as speech
amplifier with a power gain of 18 [Bar48]. This device was named transistor in 1948 - an
abbreviation of transconductance and varistor. Bardeen, Shockley and Brattain were awarded the
Nobel Prize of Physics in 1956 for this result. The first point-contact transistor was quickly
improved, mainly by Shockley himself, and he invented a new three-layer structure, which was more
robust. This structure has evolved into the famous bipolar junction transistor (BJT).
By the late 1960s, germanium was replaced by silicon with a much higher reliability and at a less
expensive cost [Mul86]. At the same time was developed surface chemistry and first high-purity
MOS layers, with the first available discrete MOS devices (1964, Fairchild and RCA companies).
Figure 1.5: John Bardeen (1908-1992), William Shockley (1910-1989) and Walter Brattain (1902-
1987) from Bell Laboratories, in 1947 (left), and the first germanium point-contact transistor (right).
The integrated circuit is a direct consequence of planar silicon technology development. The first
CMOS (complementary MOS, inc. both n-type and p-type devices) integrated circuit was realized by
Fairchild in 1962 and was a 2-transistor MOS inverter (see Figure 1.6). This technique immediately
had a lot of success. Strong improvement in photolithography, initially conceived for printing works,
was made at that time.
In comparison, an Intel Pentium 4 micro-processor picture (2004) is also proposed in Figure 1.6. On
January 2006, the first 1-billion transistor chip was released by Intel [Nai05], using a 45nm
technology node for the integration. This processor belongs to the dual-core Itanium 2 serie, with
less than 100W of total power dissipation.
Figure 1.6: First integrated circuit [Aug83] produced at Fairchild Semiconductor (left), and an Intel
P4 micro-processor, including millions of transistor in a 90nm process technology node (right).

CMOS scaling and nano-scale CMOS 17
1.3.3 Moore’s law and scaling rules
Moore’s law: an industry driver
At the beginning of the 1960s, semiconductor device performances yearly increased. Gordon E.
Moore, who was at that time R&D manager at Fairchild Semiconductor, observed this evolution. He
deduced in 1965 [Moo65]: The complexity for minimum component costs has increased at a rate of
roughly a factor of two per year. Certainly over the short term this rate can be expected to continue,
if not to increase. [...] That means by 1975, the number of components per integrated circuit for
minimum cost will be 65’000.
His vision was very pragmatic. He made different graphs and checked the time evolution of number
of transistors per chip and the relative manufacturing cost per component. He deduced that there is an
optimal level of complexity, and this level is multiplied by two each year. An example of Moore’s
law for Intel processors is presented in Figure 1.7. In this plot, the evolution in terms of transistors
per chip is shown, starting from the 4004 processor (CPU=740kHz, 2250 transistors) to the Itanium 2
Montecito processor (CPU=1.6GHz, 1.72x10 9 transistors).
Figure 1.7: Moore’s plot for Intel processors. The number of transistors per chip is plotted as a
function of time [Int07a].
In 1975, Moore revalued his prediction [Moo75]. He said that the main factors responsible for the
increase of the number of transistors per chip are the following:
• The area of the integrated circuit
• The resolution of the photolithography used
• The component and circuit design
From 1975 his view slightly changed. He said that the complexity of integrated circuits will not
double every year, but every two years, however the exponential growth remains. In his latest
contributions in 1995 [Moo95] and 2003 [Moo03], Moore observed that the advance made has
always been respected during more than 40 years.
The question that everybody has in mind is: how long will this prediction be true? There are different
ways to plot Moore’s law: for example as a function of transistors per chip or as a function of device
size. The continuous scaling down has already reached mesoscopic size, and atomic dimensions will
certainly be obtained in a couple of years. Smallest MOS devices are by now sensitive to quantum
fluctuations (random doping, Coulomb oscillations).
The International Technology Roadmap for Semiconductor (ITRS), a non for profit entity of
industry, suppliers and academic groups, is yearly publishing predictions on CMOS process
integration, devices and structures [Pid06]. The 2006 ITRS release cannot give any manufacturing
solutions for technology nodes which where preliminary supposed to be introduced in 2008! Due to a
higher and higher pressure on academic and industrial research groups, success and new results are
still reported. For example, Intel introduces in 2007 the 45nm technology node in production
[Int07b]. The 22nm node is expected around 2015.

18 CHAPTER 1: Introduction
We can reasonably imagine a scaling down up to 3 to 5nm channel length. Smaller dimensions
inevitably seem to lead to unavoidable S/D carrier tunneling.
So what can be expected is first a continuous scaling of dimensions down to an optimal channel
length size. After, performances will not result from scaling anymore, but from device optimization
and hybridization:
• New materials (high-k, metal gate, strained silicon) and new architectures (multiple gate)
• Introduction of new class of devices (carbon nanotubes, SET, spin-based transistors)
• Different computing (parallel architectures, fault tolerant circuits)
Any prediction of the end of Moore’s law is therefore extremely difficult. Other issues like power
dissipation or interconnects also have to be addressed. All these points have to be solved with an
ever-reduced manufacturing cost. A direct consequence of IC evolution is that only a very limited
number of companies will have the potential to properly integrate devices at atomic scale with
working and reliable functions.
CMOS scaling rules
Scaling of MOSFET to smaller dimensions is needed in order to increase performances:
• Higher circuit density
• Reduced power consumption per operation
• Faster circuit operation
The main physical effect that appears when reducing the dimension at submicron scale is the
electrostatic potential transformation from a 1D profile into a 2D profile [Pan04]. In a long transistor
(L>1μm), the surface potential Ψ S below the gate is constant along the channel. This is not true in
short channel devices.
Scaling parasitic effects are the short channel effect (SCE) or the drain-induced barrier lowering
(DIBL) that affect the conduction in short devices. Other issues, like the access S/D resistance or the
polysilicon depletion need also to be addressed and will be discussed in the Section 1.3.4.
Different models have been proposed to evaluate which scaling rules should be used, for horizontal
and vertical dimensions, layer thicknesses, material doping and applied voltages. The constant
electrostatic field scaling - introduced by Dennard [Den74] - is the simplest rules set proposed to
avoid reliability problems. This consists in keeping a constant electric field (vertical and lateral) in
the device. These rules are summarized in Table 1.2.
TABLE 1.2: SCALING RULES AT CONSTANT GATE OXIDE ELECTRIC FIELD [TAU98].
Scaling assumptions
Derived scaling device
parameters
Derived scaling circuit
parameter
MOSFET device and
circuit parameter
Device dimensions (L - W - x j - T ox )
Doping concentration (N a - N d )
Voltage (V D )
Electric field (E)
Capacitance (C=εA/T ox )
Inversion-layer charge density (Q i )
Current (I)
Circuit delay time (τ ~ CV D /I D )
Circuit power dissipation (P ~ V DI D)
Circuit density (~ 1/A)
Power density (P/A)
Scaling Factor
(α>1)
Major difficulties of scaling are the more and more reduced planar dimensions (L, W), and so the
need for better lithography. The decrease in the gate oxide thickness T ox (gate leakage) and the S/D
junction depth x j (ultra shallow junctions) are in addition to these technical challenges [Lo99].
1/α
α
1/α
1
1/α
1
1/α
1/α
1/α 2
α 2
1

CMOS scaling and nano-scale CMOS 19
Furthermore, a non-linear scaling is slightly introduced, as recently reported by Dennard himself in
[Den07]. As shown in Figure 1.8, a device scaling with a higher electric field - compared to the
previous node - results in an increased power density, even if power density should ideally not be
increased. This is now a big subject of concern.
Figure 1.8: Scaling of the electric field vs. channel length (left) and the projected power density vs.
frequency operation (right). Both graphics are from [Den07].
Good scaling rules
In addition to Dennard’s rules, authors [Sko00] have introduced so called good design rules which
are ideal proportions for a planar MOS device that give good performances. At nano-scale, these
rules need to be very carefully checked and are progressively not respected anymore. In the set of
equations (1.1), T dep is the depletion depth, V TH the threshold voltage and V DD the supply voltage.
xj ---
L
=
1
--
3
TOX --------
1
= -----------------
L 30 ÷ 40
Tdep ---------
L
1.3.4 Nano-scale CMOS: problems and solutions
Many anomalous scaling effects appear at submicron scale. The problem and solution list proposed
in this section does not include new device architectures (as SOI substrates or multi-gate
architectures), this part will be presented in detail in Section 1.4 of this introduction. This list of
problems and solutions is quite long, but this will serve as a reference in the MOS/SET hybrid cointegration
part. The single electron transistor is indeed so strongly coupled and dependent from the
CMOS technology, that any CMOS improvement can be beneficial for the SET integration.
In order to illustrate latest success of short-channel MOS transistors, Figure 1.9 presents three
noticeable results published recently. All these devices are operational.
L=20nm L=6nm L=4nm
Poly
gate
(a) (b) (c)
Figure 1.9: Three examples of ultimate device integration with ultra short channel dimensions.
(a) 20nm gate length, 1.2nm gate oxide thickness integrated by CEA-LETI, 2000 [Del00].
(b) 6nm gate length transistor on a SOI substrate, realized by IBM, 2002 [Dor02].
(c) 4nm gate length on bulk silicon, reported by NEC Electronics, 2003 [Wak03].
=
1
--
3
V TH
---------
V DD
=
1
--
5
(1.1)

20 CHAPTER 1: Introduction
Short channel effect (SCE)
The short channel effect (SCE) is an electrostatic effect that appears in submicronic-length transistors
[Gau03b]. As explained in Figure 1.10, the surface potential Ψ S induced by the gate voltage bias is
constant alongside the channel. At contact sides, the voltage is equal to the built-in voltage V bi at the
source and V bi + V DS at the drain. The SCE is calculated at V DS =0.
Short channel devices do not have a constant surface potential. This is due to the proximity influence
of S/D sides, resulting in a 2D potential distribution below the gate. The shorter the device, the
smaller the S/D potential barrier.
The consequences of SCE are a negative shift of the threshold voltage V TH worsened by a higher
dispersion value. The second major consequence, linked with the un-scalability of the sub-threshold
slope, is a net increase of the I OFF current [ I OFF =I D (V G =0) ].
The influence of the short channel effect is calculated with equation (1.2), this gives the barrier
potential lowering (in Volt) at V DS =0 (see Figure 1.10).
Ψ S [V]
2.0
1.5
1.0
0.5
DIBL
Ψ S = V bi +V DS
DIBL
SCE
SCE
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6
Channel length [μm]
Ψ S = V bi
Figure 1.10: n-channel MOSFET surface potential with different channel lengths. Short channel
devices may suffer from both short channel effect and drain induced barrier lowering.
The short channel effect is expressed with the following equation [Sko05]:
2
xj SCE 0.64 εSi ⎛ ⎞Tox ------ ⎜1+ ------ ⎟-------
ε 2
ox ⎝ ⎠ Lel Tdep = --------- V
L bi = 2 × EI × Vbi el
L el
L el is the electrical channel length, this is the distance between the two source/channel and channel/
drain junctions. T ox is the gate oxide thickness and T dep the depletion depth in silicon. EI stands for
Electrostatic Integrity.
The decrease in threshold voltage, called V TH roll-off, is given by the following equation:
ΔV TH
qNATdepxj⎛ 2Tdep ⎞
=
– ------------------------ ⎜ 1 + ------------- – 1⎟
CoxLel ⎝ xj ⎠
These two equations will be used in further sections of this work.
Solutions to limit the short channel effect exist and they consist in modifying the 2D electrostatic
potential below the gate into a 1D constant profile, as it is the case in long channel devices. The main
solutions proposed in the literature are:
• Thinner gate oxide
• Non-uniform lateral channel doping (called superhalo doping) [Tau97]
• Very abrupt S/D junctions
• The use of fully depleted SOI substrates (see Section 1.4)
• Negative substrate bias (to limit V TH roll-off)
0.7
(1.2)
(1.3)

CMOS scaling and nano-scale CMOS 21
Modeling of SCE can - for example - be calculated with MASTAR [Sko93], an executable code
developed along with the ITRS [Mas07]. It uses the voltage-doping transformation [Sko00].
Drain induced barrier lowering (DIBL)
The drain induced barrier lowering (DIBL) is an electrostatic issue resulting from a non-uniform
potential distribution below the gate, due to S/D implantation proximity. The potential barrier in
short channel transistors is linearly modulated by the drain-source bias (see Figure 1.10). This leads
to an increase in electron injection from source to drain, and so to a sub-threshold current increase
[Sko00]. Solutions proposed to limit the DIBL are the same as those applied for the SCE.
DIBL 0.8 εSi ⎛ ⎞Tox ------ ⎜1+ ------ ⎟-------
ε 2
ox ⎝ ⎠ Lel Tdep = --------- V
L DS = 2 × EI × VDS el
Channel doping and anti punch-through
S/D
extension
p- bulk
Figure 1.11: Typical doping profile for a planar
sub-100nm channel length NMOS device.
The different doping profiles have to preserve the Electrostatic Integrity, and to limit short channel
effect and V TH roll-off. The p+ retrograde doping is a S/D anti punch-through artefact. This serves to
avoid the breakdown of the S/D junction through the bulk of the transistor, at high V DS bias.
The implantation control has to be extremely precise at the nano-scale size. Different species are
used (P, As, B, BF 2), at low energy (a few keV) and at high dose - in order to have ultra shallow
junctions. Different activation methods are proposed to limit as much as possible dopants diffusion;
we can mention RTA (rapid thermal annealing) and LTA (laser thermal annealing). Many
technological variants are investigated [Fra01].
Random fluctuations
A long-channel
MOSFET
Spacer
Gate
2
xj L el
n++ n++
n+ n+
p+ pockets
p+ retrograde doping
A 22nm MOSFET in
production 2008
p channel
doping
A 4.2nm MOSFET
in production 2023
Figure 1.12: Effect of matter discreetness at
nano-scale. Picture from [Ase03].
Threshold voltage variations ranging from 20 to 40mV have been reported in sub-50nm channel
length devices [Asa97]. The concept of un-doped channel has also been proposed in order to avoid
fluctuations.
(1.4)
As given in Table 1.2, the silicon doping level
has to increase with channel size reduction.
Figure 1.11 shows an example of doping profile
in a n-type short channel device. The following
dopants are implanted during the process:
• n+ doping at S/D for ohmic contacts
• n++ S/D extensions (low access resistance)
• p channel doping (V TH adjustment)
• p+ pockets (SCE, V TH roll-off) [Coc99]
• p+ doping (to avoid S/D punch-through)
Random dopant fluctuation will be a major
issue in the next decades for the integration of
nano-scale devices. Discreet aspect of matter, as
displayed in Figure 1.12, affects reproducibility
among devices. A poor device matching will
have a large impact on circuit design.
The 7nm node, predicted by the ITRS for 2025,
has a channel made up with only 15x15x15
silicon atoms. The impact of any single dopant
or single defect will have direct consequences
on electron transport, and mainly on V TH
fluctuations [Miz94].

22 CHAPTER 1: Introduction
Mobility degradation
Current in electrical devices linearly depends on carrier mobility in silicon. The higher the mobility,
the higher the current. Typical values reported in un-doped bulk silicon are:
• Hole mobility ...................................................................... μ h = 471 cm 2 /Vs
• Electron mobility................................................................. μ e = 1417 cm 2 /Vs
These mobility values are not effectively observed in MOS devices. Carrier mobility in silicon
devices is only a fraction of bulk values and is limited by the following effects:
• Applied electric field: mobility degradation by phonon scattering (Mathiessen rule).
• High doping level degradation (μ e ~ 50 cm 2 /Vs at N D =10 20 cm -3 ).
• Interface scattering at the Si/SiO 2 interface of a MOSFET.
As scaling is done at constant electric field, mobility degradation is limited in short channel devices.
However, the high doping level of bulk substrate and the difficulty to have highly clean interfaces at
the nano-scale does not help to maintain this high level.
Different empirical laws are proposed to take account of mobility degradation. General description
can be found in [Mul86]. Phonon scattering model is proposed by [Lom88] and doping-dependent
mobility reduction in [Mas83]. Concerning surface scattering in ultra-scaled devices, reports
proposed are more controversial. Similarly, the exact value of mobility in short channel devices is
still under investigation. Further developments are given in this 2006 paper [Ern06].
Strained silicon
The strained silicon technique consists in inducing stress in silicon to enhance carrier mobility. The
silicon bandgap is also changed by an applied stress. Depending on silicon crystalline orientation and
doping level/type, a gain in mobility of a few tenths of percents is obtained for less than 1% of strain
(tensile stress for NFET, compressive stress for PFET). Almost all advanced CMOS technologies are
exploiting mobility enhancement in strained silicon.
A remarkable study of strained ultra-scaled devices integration is given by [Rim00]. A TEM picture
of a strained silicon channel is shown in Figure 1.13. Introduction of strain in silicon is a very
efficient way to improve performances, which are directly observed in a net increase in the device
transconductance g m. Systematic extraction of the inversion layer mobility vs. strain in nano-scale
devices was recently proposed by [Iri04]. This reference is valid for n-type and p-type inversion
layers with different crystalline orientations.
Figure 1.13: Example of a transistor with a 65nm long strained silicon channel. Strain is obtained
from the combined use of a SiGe buffer layer and S/D silicidations. Picture from [Lee05].

CMOS scaling and nano-scale CMOS 23
Strained silicon is also used in non-CMOS silicon applications, for example in sensors or NEMS. An
example of giant piezoresistive effect measured in a silicon nanowire is shown in Figure 1.14. This
device emphasizes a different strain behavior in silicon at the nano-scale, in comparison with larger
structures. The test structure used is a CVD grown silicon nanowire, using Au nanoparticle as
the catalyst and anchored between two silicon pads.
Figure 1.14: Piezoresistance effect measured in a -oriented, p-type, grown silicon nanowire,
according to [He06].
The main techniques proposed to induce strain in silicon are:
• Lateral source drain silicides
Silicidation of S/D contacts results in stress in the channel. This depends on silicide type, channel
length and device structure. Excellent PMOS (compressive stress), with low access resistances, have
been reported.
• Over-layer deposition (nitride)
CVD and PECVD deposition of nitride layer can induced >1GPa of internal stress, both tensile or
compressive. Stress distribution highly depends on the device structure.
• Stress induced by oxidation
SiO 2 is a viscoelastic material. Silicon oxide growth induces stress in the structure [Shi00]. This
effect is not really well-adapted for CMOS technology but is of crucial importance in single
electronics, as further explained.
• The use of a SiGe buffer layer
Crystalline lattices of SiGe and Si are different. Epitaxial growth of Si over a SiGe layer results in a
strained silicon layer. Furthermore, SiGe can be selectively removed by dry etching.
A detailed review on the techniques used to produce strain in CMOS technology is presented in
[Chi06]. As reported on other works, [Chi06] describes also the stress memory technique (SMT),
which is a combined effect of implantation-controlled S/D silicon amorphization and nitride overlayer
deposition to induce stress in silicon. Stress can be stored in the doped S/D junctions, if an
adapted annealing process is introduced in the process flow. SMT has the advantage that silicon
strain level is maintained even after removal of the nitride layer. This is now highly used in PMOS
fabrication.
Gate oxide leakage, high-k dielectrics
Gate
C OX
Silicon
3nm
D
IDS S
500nm
Poly-Si
HfSi x O y
Si(100)
Figure 1.15: MOS capacitor made with Poly-Si
as a gate, HfSi xO y as dielectric material and
silicon substrate. Picture from [Wil00].
The dielectric layer between the gate and
silicon has to be perfectly controlled, in terms
of thickness, material composition and
cleanliness.
Advanced technologies are now using only few
nanometer thick gate oxides, this means only a
few atomic layers. This results in unavoidable
gate tunneling current leakage. New dielectrics
are therefore investigated to replace SiO 2 by a
thicker dielectric material, with a higher
permittivity ε, as shown in Figure 1.15.
The gate leakage phenomenon is a very annoying effect in scaled-down technology. At V G =1V, a
defect-free gate-to-channel capacitor with 3nm of SiO 2 is leaking ~10 -12 A/μm 2 , while the same

24 CHAPTER 1: Introduction
capacitor with 1nm of SiO 2 is leaking ~10 -4 A/μm 2 [Sko05]! Limited leakage is accepted, the
maximum is approximately reached when I GATE =I OFF . A complete description of scaling effects on
gate leakage current, including current modeling, is presented in [Wat03].
High-k dielectrics modeling is based on the following two equations. The use of high-k dielectrics
preserves the gate oxide capacitance C ox but the tunneling leakage current J G decreases rapidly.
C ox
k ε0 = ----------
JG α exp(
– Tdiel ⋅ φB) T diel
T diel represents the dielectrics thickness, k the relative permittivity of the dielectric (the k-constant of
SiO 2 is 3.9, the k-constant of Si 3 N 4 is 12) and Φ B the potential barrier height measured between the
dielectrics top band and the silicon conduction band. The gate leakage current is derived from
Fowler-Nordheim’s theory of tunneling.
Parameters to take into account for the choice and integration of a high-k dielectric material are:
• High permittivity (typical k-values are ranging from 10 to 30)
• High potential barrier Φ B to keep current leakage low (high band-gap material)
• Minimized defects and charge trapping in the film
• Film morphology: amorphous and epitaxial films are preferred as poly-crystalline layers
• Process compatibility in a CMOS integration (no thermal degradation)
• Precursor availability (atomic layer deposition or CVD)
• Reliability (ageing of the film caused by injected carriers and high electric field)
• Integration cost
Only a few dielectrics materials fulfill these requirements. Dielectric stacks of SiO 2 and high-k
material are often used because Si/SiO 2 is an excellent channel interface and avoids silicon mobility
degradation. Typical materials used in DRAM manufacturing are Ta 2 O 5 HfO 2 or Al 2 O 3 . Intel’s
45nm node is successfully using hafnium silicide as a gate dielectric material [Int07b]. The reference
[Wil01] is a very complete review article on high-k dielectrics integration and performances.
Polysilicon gate depletion, metal gate, gate stacks and silicides
Polydepletion
2D electrons
in the gate
Equivalent oxide
thickness
SiO 2 barrier
Darkspace in
the channel
2D electrons in
the channel
n+ poly gate p Si substrate
Figure 1.16: Schematic of electrons distribution
in a n+ poly / SiO 2 / p-silicon stack. The
equivalent oxide thickness is much larger than
the physical SiO 2 thickness.
The poly-depletion and darkspace effects cannot be neglected. They reduce the electrical gate oxide
capacitance C ox and so limit device performances (sub-threshold slope, I ON current). Darkspace
results from physical carriers quantization in a 2D plane and cannot be avoided. On the contrary,
poly-depletion can be eliminated with the integration of metal or silicide as gate materials.
(1.5)
The material commonly used for the gate of
MOS devices has been polysilicon during many
years. This material has many advantages, like
very easy in-process integration, excellent
thermal reliability and the dual p/n gate doping
necessary in CMOS technology.
The trend has now changed. At the nano-scale,
polysilicon suffers from the poly-depletion
effect. This parasitic effect is a depletion of
carriers due to gate bias.
As explained in Figure 1.16, a n+ poly gate
used for a NMOS device gate has electron
depletion at the gate - gate oxide interface.
Furthermore, as the inversion charge in a 2D
MOS interface induces also a darkspace in the
channel, this results in an equivalent increase in
gate oxide thickness. The Equivalent Oxide
Thickness (EOT) is the sum of poly-depletion
depth, gate oxide thickness and silicon
darkspace.

CMOS scaling and nano-scale CMOS 25
Metal gates are often combined with high-k dielectrics. They also have the advantage to lower the
gate sheet resistance, in comparison with polysilicon. This is of particular interest in AC
applications. Unlike metal gates, polysilicon gates need to be doped (in-situ, by implantation or
diffusion), and induce a doping gradient in the gate oxides, that can make them leaky.
The choice of a metal for gate integration is limited. In order to have a symmetric threshold voltage
for both NMOS and PMOS devices in a CMOS technology (V TH_NMOS =-V TH_PMOS ), a N+ -like
metal is needed for NMOS devices, while P+ -like are needed for PMOS. This is given with the
work-function of the metal used. Typical N+ metals are Al, Ta, Ti, Cr or Mo. The choice for P+ gates
is more limited, with candidates like Pt, Re and Ir. A dual-metal gate technology for deep-submicron
CMOS transistors example is presented in [Qia00].
Alternatives to polysilicon and metal exist with gate silicidation. A silicide is a compound material of
silicon and metal (CoSi 2 , NiSi 2 , WSi 2 ). Silicide gates usually have a mid-gap work-function and can
be considered for both NMOS and PMOS transistors. This is much cheaper, faster and easier to use a
single gate material in a CMOS technology platform. The report [Mas02a] is of high interest and
presents an extremely smart gate silicidation in CMOS technology.
The effect of threshold voltage control in metal/silicides gates, due to work-function variation, can be
tuned with a proper substrate doping. Therefore, the integration of metal or silicided gates is a
technology booster, that will more and more be exploited in CMOS technology.
Access resistances
Ideally, the conductance of a MOS transistor depends from its channel resistance only. As device
geometries are scaled down, the different channel access resistances are not negligible anymore. As
displayed in Figure 1.17, the typical access resistance is shared between metal/silicon R contact ,
source and drain R S/D and overlap region below the spacer and the gate R overlap .
An applied ideal scaling (see Table 1.2) dictates that the channel access resistance should remain
constant. In practice, this is almost unfeasible, mainly due to doping control and limited solubility of
dopant atoms.
Gate Spacer
Metal
R channel R overlap RS/D
Si-bulk
R contact
Figure 1.17: Scheme of different channel access
resistance contributions.
Ballisticity and source/drain leakage
The major solution developed to keep ohmic
low-resistance contacts is a tight control of the
S/D region doping.
Solutions are coming from implanted ultrashallow
junctions combined with rapid thermal
annealing (RTA) to limit dopants diffusion as
much as possible. S/D silicidation or elevated
contacts (epitaxial silicon, silicon CVD, SiGe
CVD) are also proposed and successfully
realized.
A detailed study of the role of access
resistances is proposed by [Osb98]. We can also
add, that any type of nano-scale devices (MOS,
but also emerging devices, as further explained)
usually cause contacting difficulties.
A ballistic MOS is a device, where carrier transport from drain to source occurs without any
scattering within the silicon lattice i.e. when the carrier mean free path is longer than the channel
length. In short channel devices, a ballisticity rate is measured to be up to 50%. However, current
MOSFET are essentially classical devices.
Ballistic equations of a MOS devices are usually based on the resolution of non-equilibrium Green’s
functions (NEGF) [Dat02]. The two opposite trends in ballistic devices study are on one hand, that
I ON current is higher than in ohmic channel transistors, but on the other hand, short channel devices
may have leaky S/D tunnel conduction even if the device is turned OFF. Short channel devices with a
high ballisticity rate may have enhanced performances, but they will not be fundamentally better. An
in-depth study of carriers transport in nano-scale devices is proposed by [Lun02].

26 CHAPTER 1: Introduction
Invariability of the sub-threshold slope
High I OFF
Drain current,
Log(I ) D
I OFF negligible
V TH reduction
V TH
Figure 1.18: Effect of the invariability of the
sub-threshold slope on devices scaling.
The sub-threshold slope is given by the following equation:
A steep subthreshold slope is a direct signature of a performing technology. Unfortunately, as given
by Equation 1.6, the maximum S-slope at room temperature is about 63mV/dec and does not depend
on dimensions. This means that a gate bias >378mV is necessary to turn ON a transistor if 6 decades
on I ON/I OFF are needed.
High performance devices, using ultra-thin gate dielectrics, have a subthreshold slope which is
almost equal to the best achievable. However, as reported by [Gwo02], the S-slope is degraded in
ultra-scaled channel length transistors. This is attributed to the 2D electrostatic profile distribution,
also responsible for SCE. Finally, as explained in the next section, new 3D MOSFET architectures
are often very efficient S-slope boosters.
Noise and device scaling
Equivalent
sub-thresold
slope
L=50nm
Gate voltage, V G
Increased I ON
L=5μm
S ( 10)
kT εSi ⋅ Tox =
ln----- ⎛1+ --------------------- ⎞ ≥ 60mV ⁄ dec
q ⎝ εox ⋅ T ⎠
dep
The sub-threshold slope (S-slope) is an essential
parameter for the use of the MOS as a lowvoltage,
low-power switch.
The I ON /I OFF ratio of a MOS has to be as large
as possible, ideally 6 decades or more. As
shown in Figure 1.18, a reduction of
dimensions increases both ON and OFF
currents.
However, the threshold voltage is reduced with
channel length scaling, and this results in a
dramatic OFF current increase.
(room temperature) (1.6)
Electronic noise is parasitic random current variations, exhibited by any electronic devices. There
are different types of noise. Main ones are shot noise, thermal noise and flicker noise (1/f noise).
Scientific definitions of noise in a solid material can be found for example in [Kog96].
Regarding the question of scaling, the noise problem cannot be ignored. In many nano-CMOS
references, there is nothing or only a few comments on noise. Any scaling effort may be lost if the
signal-to-noise ratio (SNR) increases with scaling.
However, some authors have focused a lot of effort on scaling and noise, and especially on flicker
noise. It was found that the noise level increases with scaling, but due to the current increase, SNR
ratio decreases. So scaling can be considered as a good way to reduce noise in devices and circuits.
For example, the paper [Che04b] proposes a study on flicker noise for channel length ranging from
350 to 130nm, with the conclusion that the shorter the channel, the better the SNR ratio. This paper
has also highlighted the effect of oxynitride dielectric as a possible 1/f noise origin. It describes the
role of nitrogen atoms at Si/SiO 2 interface as a noise generator due to a higher scattering level. As
previously explained, high-k dielectrics are almost unavoidable technology boosters, but may
introduce more noise in the channel. Further discussions in the field of noise vs. scaling and a better
understanding of the origins of noise are of high importance for nano-CMOS devices 1 .
1. Even if noise is a noisy subject for many people. (Author’s note)

Tri-dimensional MOSFET structures 27
1.4 Tri-dimensional MOSFET structures
The previous Section: CMOS scaling and nano-scale CMOS reviews current limitations and gives
main ideas to increase device performances, by new materials integration. On the contrary, this
Section: Tri-dimensional MOSFET structures will focus on new architectures that are used in nano
CMOS. The planar bulk geometry is the simplest design that can be used for a field-effect transistor.
There are now many studies on tri-dimensional (3D) MOSFET architectures. Some examples are the
silicon-on-insulator (SOI) MOSFET, the FinFET and the Gate-All-Around geometry. In most
advanced technologies, a combined use of new materials and new architectures is exploited. Tridimensional
MOSFET architectures can address the following issues:
• Short channel effect and DIBL: better electrostatics (2D to 1D potential distribution)
• Higher cut-off device frequency (increased CV/I)
• Increased device width without consuming large chip area
• Double or multiple independent gates on a same device
• Better sub-threshold slope
• Lithography-free short channel devices
• Integration of strained silicon layers
• Immunity against radiations
• Latch-up prevention (parasitic bipolar effect in the bulk)
There are as many technologies as 3D devices! However, the price to pay for non-planar bulk
architectures is usually a higher cost (SOI substrates), an increased number of integration steps, new
difficulties in etching (deep straight trenches), layer deposition (cavities filling) or photolithography
(due to topography). In terms of characterization, 3D devices may suffer from self-heating (on the
contrary, heat conduction on planar silicon bulk is excellent), from parasitic fringing effects or from
kink effect (well-known effect in partially-depleted SOI).
1.4.1 Silicon-on-insulator (SOI)
Silicon-on-insulator is a technology that uses a substrate made up with a stack of a silicon substrate,
a buried oxide and a thin silicon top layer to build active devices (Figure 1.19). This is now a major
technology for next CMOS generations. There are different techniques to fabricate SOI substrates. It
was based initially on silicon-on sapphire (SOS). Since the early 1980s, this was mainly replaced by
SIMOX (separation by implantation of oxygen), BESOI (bond and etch-back SOI) and, more
recently, the so-called smart-cut technique. SIMOX is used for ultra-thin silicon layers while BESOI
is preferred for thicker silicon layers.
The crystallinity of the film, thickness variation, doping control and interfaces quality are of crucial
importance in SOI MOSFET integration. A review of the different SOI wafers production methods
are described in [Kuo98]. The literature on SOI-based devices and circuits applications is rich and
well-documented.
n+
Gate
p
Silicon substrate
Figure 1.19: Basic architecture of a n-type SOI MOSFET.
n+
Silicon
top layer
Buried
oxide

28 CHAPTER 1: Introduction
The ITRS [Pid06] is deeply focusing on SOI MOSFET, and particularly on fully depleted (FD) ultra
thin body (UTB) SOI transistors for logic applications. UTB SOI consists of a silicon film as thin as
10nm in the device channel region. Combined with ultra-thin gate oxide, this is a nice solution to
retrieve a good electrostatics, and so to limit both SCE and DIBL ([Dor02] L channel =6nm) and to
improve S-slope ([Dor03] S-slope=77mV/dec, L channel =8nm, SOI thickness T Si =8nm).
Designers propose to use a thin BOX layer and a highly doped silicon substrate to limit SCE, DIBL
and device self-heating [Fen03]. Experiments on devices with as thin as 5nm of T Si have also been
proposed [Uch02] and show an interesting electron mobility increase. However, UTB SOI MOSFET
threshold voltage is highly sensitive to T Si variations and is a very difficult technology.
1.4.2 Double-gate, FinFET and Silicon-on-Nothing
The three types of devices presented in this section have all a double channel current flow, which is
parallel to the surface of the wafer. They also all offer a higher equivalent width for a limited wafer
surface use. The so-called Double Gate structure has two distinct gates that can either be controlled
individually (independent gates) or not (tied gates). On the contrary, the FinFET and the silicon-onnothing
(SON) have a single gate which controls two Si/SiO 2 interfaces. In the FinFET and SON,
conduction in the silicon corners is negligible, due to the channel aspect ratio or spacer isolation.
D
Double Gate
Figure 1.20: Double-Gate, FinFET and Silicon-on-Nothing device geometries.
As shown in Figure 1.20 (left), a double-gate transistor is a device with two parallel gates. As in SOI
devices, an ultra-thin channel silicon thickness results in a fully depleted device, a thicker one in a
partially depleted device. The best electrostatics is observed in UTB double gate transistors, with
limited SCE and DIBL, and also with a good S-slope. This results from the top gate - bottom gate
charge coupling [Fos02]. Both simulated and measured speed performances are better than singlegate
SOI. The comparison factor with planar CMOS is the C oxV DD/I ON (CV/I) constant.
In SOI, the substrate can also occasionally acts as a second gate, but with poorer performances, due
to the thick BOX thickness and the non-controlled quality of the BOX/SOI interface. The operating
mode of an independent double-gate transistor consists in tuning the threshold voltage (dynamic V TH
control) with one gate and switching the transistor with the second one [Yan97]. A dynamic control
of V TH leads to a lower OFF current.
Different fabrication technologies are proposed. Wafer bonding is an efficient technique but this is
costly and extremely difficult to perfectly align the two gates. A process description and
misalignment issues are discussed in [Wid04]. Auto-aligned single-wafer processes are also
proposed, for example [Zha03] uses this technique. Unfortunately, in the report of [Zha03], the
channel is a deposited amorphous silicon with a reduced mobility. Auto-aligned double-gate
transistors integrated with a 25nm Si epitaxial growth have successfully been realized [Won97]. The
challenges for an optimal double-gate integration are (i) a uniformly, thin (10 - 25nm) Si channel, (ii)
a low access S/D resistance and (iii) a perfectly aligned (ideally auto-aligned) top-bottom gates
technique.
FinFET
I DS
Top Gate
Bottom Gate
S
Double Gate
BOX
Si
substrate
I DS
Fin Gate
Si epitaxial
bridge
D
Si substrate
FinFET Silicon-on-Nothing
The FinFET is a possible double-gate architecture. It consists of a thin and high trench (called fin) of
silicon etched in a SOI wafer. Then a gate is wrapped around the channel, as shown in Figure 1.20
(center). Usually, a hard mask or a thick dielectric layer is kept over the fin to cancel any conduction
Gate
I DS
S
STI

Tri-dimensional MOSFET structures 29
on the silicon top interface. The current flows at the Si/SiO 2 interface on both the lateral sides of the
trench. An efficient feasibility of sub-50nm channel length FinFET has been recently (2001)
demonstrated [Hua01]. The high interest on FinFET is the consequence of some unique
characteristics of this architecture:
• The two lateral gates are always auto-aligned (a single gate shared on the two sides)
• Raised S/D contacts with low access resistance
• Excellent short channel behavior (down to 10nm)
• High-current devices with parallel Fin structures
• Overall dimensions are very limited
For the moment, as in all 3D MOSFET architectures, many different technological approaches have
been proposed. The main drawbacks of the FinFET are the difficulty to lithographically define and to
etch thin and short silicon trenches on SOI wafers. Electron-beam lithography followed by resist
trimming and oxide hard-mask trimming allow to obtain as small as 20nm fin width [Cha03].
Some valuable alternatives to the FinFET have also been very recently investigated. For example,
Toshiba has developed a sidewall transfer process [Kan05] for sub-15nm channel length and 10nm
fin width with a double fin density. The same group [Oka05] has also proposed a FinFET on bulk
(L channel =20nm, Fin_height=6nm) with resist trimming and sacrificial oxidation in their process.
Finally, it was presented an operational 5nm channel length nanowire FinFET [Yan04], with a special
focus on full 3D quantum simulation of the device.
Silicon-on-nothing
Silicon-on-nothing (SON) is an innovative process developed by ST Microelectronics at the end of
the 1990s. The fabrication process, done on bulk Si wafer, is based on the epitaxial growth of a
silicon ultra-thin nano-bridge over a SiGe layer. Then, as displayed in Figure 1.20 (right), the silicon
bridge is released from SiGe and a gate wrapped around the two sides of the silicon bridge is defined.
Voids are filled with oxide, resulting in a local-SOI structure, where only the region below the
channel is isolated from the silicon substrate [Jur00].
The SON process is taking a lot of advantages of the efficient growth of Si layer over a handling
SiGe layer, and to the possibility then to selectively remove SiGe by isotropic dry etching. As Si and
SiGe do not have the same lattice constant, the grown Si layer is under stress, resulting in a possible
higher carrier mobility. Strained silicon is exploited in the SON process, as well as in other
technologies. [Che04a] and [Ali00] have for example proposed Si/SiGe multiple layers as a new
material architecture, using Si quantum wells as MOSFET channels.
Compared to UTB SOI MOSFET, the SON process does not suffer from self-heating and has lower
S/D access resistances. Moreover, SON devices have a high immunity to SCE and DIBL, and a
close-to-ideal S-slope. SON transistors with a 80nm channel length integrated on a 20nm thick Si
epitaxial bridge have been measured [Mon01] and have about ~30% better I ON in comparison with
planar bulk CMOS. Coulomb Blockade oscillations have also been reported in SON devices
[Mon03]; this will be discussed in detail in the next sections on emerging devices.
The concept of germanium on nothing has been recently proposed. The paper [Bat07] shows how a
thin SiGe film on insulator, used as MOS channel, may improve the device electrostatic integrity.
Silicon-on-nothing is therefore a highly valuable technology, that can be scaled down to gate-allaround
geometry. However, the large number of integration steps and a high fabrication cost may
slow down SON industrialization.
1.4.3 The vertical MOSFET
In a vertical MOSFET device, the current flow is orthogonal to the surface of the wafer. A stack of
n+ p n+ silicon (in case of a NMOS device) is made by epitaxial growth or implantation; and then a
gate is defined around the structure. This architecture has proved to be a realistic approach to sub-
100nm channel length [Jos01] devices.
Since then, many different architectures have been proposed, using high-k dielectrics [Her01] or
ultra-thin silicon channel. A 15nm L channel in a vertical gate MOSFET has recently been
demonstrated by [Mas02b]. The vertical MOSFET shows better performances than bulk planar
devices and is an appealing structure, even if there is no leading design or fully optimized fabrication
process for the moment.

30 CHAPTER 1: Introduction
Gate
oxide Oxide
Gate
Oxide
Figure 1.21: A vertical MOSFET geometry, as proposed by [Her01]. The channel length is defined
by the distance between the two S/D junctions. The transistor width depends on the layout used.
An alternative architecture - called the vertical sidewall MOSFET - exploits a thin silicon trench as
channel of the transistor [Sch01]. The drain is on the top of the trench, but the source is placed
laterally, and is not buried below the channel. This process uses fewer integration steps in
comparison with a pure vertical MOSFET geometry, and S/D contacts are easier to achieve. The
compatibility with planar MOSFET is also improved.
1.4.4 Tri-Gate, Pi-Gate and Omega-Gate
Tri-gate, Pi-gate and Omega-gate are gate architecture variants, essentially originating from the
FinFET geometry, but with a larger fin width. Conduction in the top of the fin is not negligible
anymore. All these structures are characterized by a triple-side current flow controlled by a tied gate
around the channel. The merit of these different architectures has been reported the first time by J.-P.
Colinge [Par01a].
Many publications are investigating the tri-gate structure. Well-described results, including a
complete characterization of devices are reported in [Doy03]. A 36nm high and 55nm wide silicon
trench etched on a SOI wafer, with a 60nm tri-gate length has given excellent results in comparison
with planar devices. The subthreshold slope of NMOS devices is 68mV/dec and the complete
absence of kink effects indicates that the device is fully depleted. ON-current is 1.14 mA/μm while
OFF-current is very low 70nA/μm. A more general evaluation on how to keep Moore’s law living
was given at ISSCC by S. Chou [Cho05]. 3D-MOSFET geometries are focusing a lot of attention,
including the tri-gate architecture with multiple silicon channels in parallel.
Finally, a very recent contribution has successfully combined material boosters (HfO 2 high-k
dielectrics, metal gate and strain channel) in a tri-gate process [Kav06] with 40nm channel length
and excellent SCE immunity.
Pi-gate is a tri-gate structure with the two lateral gate sides extending into the buried oxide [Par01b].
The reason to extend the gate is to obtain an electrostatic as close as possible to a gate-all-around
geometry, but with a much easier integration process. If the dimension of the silicon fin is small
enough, it was shown by simulation that the lower part of the two lateral gates have almost the same
influence has a fourth back gate.
Figure 1.22: Ω-gate device schematic.
n+ top drain
I DS
p-Si
I DS
n+ bottom source
Oxide
Handling substrate
Gate
Oxide
Omega-gate is another tri-gate variant which is
the closest to the gate-all-around architecture.
The paper [Yan02] presents a 25nm channel
length tri-gate process including a notch underetched
in the buried oxide. Then a conformal
polysilicon gate is deposited, resulting in an
Omega (Ω) gate shape.
EPFL has also proposed original results for
impact ionization effects on Ω-gate devices.
This has been proposed at ESSDERC [Mos07].
A bulk Ω-device geometry is shown in Figure
1.22.

Tri-dimensional MOSFET structures 31
1.4.5 The silicon nanowire gate-all-around architecture
The gate-all-around (GAA) architecture is an advanced MOSFET geometry where the silicon
channel is completely surrounded by a gate. As displayed in Figure 1.23, three different cross-section
shapes are represented. GAA devices will be described in detail in this thesis report because this is
the geometry chosen for the co-integration of both SET and CMOS in a single technology process.
GAA are excellent devices, in terms of SCE, DIBL, S-slope and I ON /I OFF ratio. GAA main
drawbacks usually are for the moment a highly difficult fabrication process. This fabrication is often
based on the realization of silicon nanowires, acting as core of the device, and followed by gate
oxidation and gate material deposition. The channel cross-section is also crucial for the operation of
the device. A small cross-section results in a ’’volumic’’ fully depleted nanowire, while larger crosssection
operate as partially depleted. Corners in the wire (in rectangular or triangular) contribute to
corner effects, and are considered either as parasitic (double threshold voltage) or sometimes as
beneficial effects (lower threshold voltage, local volume inversion). Gate-all-around silicon
nanowires are also highly suitable structures in single electronics. A small cross-section results in a
2D carrier confined quantum wire, while an ultra-short silicon wire acts as a 3D quantum box with
discrete energy levels. Potential applications are large and will be deeply discussed in next chapters.
Channel
length
I DS
Rectangular
cross-section
Triangular
cross-section
Gate
oxide
Silicon
core
Circular
cross-section
Figure 1.23: Three geometries of gate-all-around architectures, with different cross-section shapes.
From 1990 to 2000, authors have mainly been interested in electronic properties modeling using
quantum mechanics, and many publications were still disconnected from any device applications
[Nee94]. The silicon band-gap calculation in a silicon quantum wire was proposed the first time in
1993 by [She93].
The first GAA transistor on SOI was presented very early at IEDM 1990 by J.-P. Colinge [Col90].
Despite large dimensions (W/L=3μm/3μm) and a thick 50nm gate oxide, these pioneer devices show
correct characteristics. The device fabrication is very simple. A thin SOI wire is lithographically
defined and etched, that step is followed by the release of the wire from the buried oxide. The gate
used is LPCVD polysilicon.
Another remarkable GAA MOS transistor was later proposed in 1997 by the Minneapolis University
[Leo97]. This is one of the first reports that includes a complete description of GAA performances.
Dimensions of the nanowire are in agreement with ITRS 1997 requirements. The wire has a
rectangular cross-section (50nm height x 35-75nm width), the minimum wire length is 70nm and the
gate oxide thickness is 11nm. Polysilicon is also used as gate oxide material. The characteristics
extracted are good, with a 90mV/dec S-slope. A multiple-channel design is also proposed.
Since then, many optimized designs have been reported. We can refer to [Son06] and [Suk05] as two
excellent GAA CMOS technology reports. The paper [Son06] makes a comparison between a
double-gate and a GAA geometry, and demonstrates how GAA boosts device performances. Second,
this report is also making a comparison between a rectangular and a circular channel cross-section,
showing that a cylindrical silicon channel has a much more reduced OFF current and lower SCE and
DIBL, due to the absence of corner effects. Results published by [Suk05] are also of great interest
and present a process for the integration of twin silicon nanowire MOSFET using a self-aligned
damascene process. They obtained circular 5-10nm diameter GAA devices with 30nm gate length,
resulting in a remarkably high 2.64mA/μm ON-current for n-type devices.
Gate

32 CHAPTER 1: Introduction
Finally, this is also worth to name reports which do not directly focus on advanced CMOS
applications. For example, a group from Singapore University [Sin06] has very recently (IEDM
2006) emphasized the impact of channel diameter, crystal orientation and low-temperature
characteristics on GAA device performances, showing especially the occurrence of I D -V G
oscillations at low temperature.
The last example we would like to report is a bottom-up approach proposed by [Web06]. Silicon
nanowire transistors with a diameter ranging from 10 to 30nm and nickel-silicide contacts are
successfully integrated and measured. These devices exhibit up to 7 decades I ON /I OFF ratio. The
process used by [Web06] is very innovative and shows that there is up to now no established GAA
technology.
More specific EPFL results obtained during this work are described in the next chapters. All things
considered, it really seems that the GAA is the best actual architecture to sustain Moore’s law.
1.4.6 The tunnel FET
The tunnel FET is at the boundary between advanced CMOS architectures and emerging devices. It
has the same three-terminal structure as a MOSFET transistor, but source and drain usually have an
opposite doping (p+ source and n+ drain) and the channel of the transistor is low doped (p- or
intrinsic).
The tunnel FET operates the following way: when the p-i-n diode is reverse-biased, the gate controls
band-to-band tunneling from the valence band in the heavily doped p+ source region to the
conduction band in the channel. The vertical architecture has often been proposed for easier process
integration. An interesting report on tunnel FET scalability is reported in [Bhu05], including device
structure and simulation. Advantages reported in this architecture are:
• A perfect I D -V D saturation
• An exponential I D -V G dependence
• A quasi-free current temperature dependence
• A very low I OFF (

Technology hybridization with emerging devices 33
1.5 Technology hybridization with emerging devices
The last section of this introduction is a study of emerging devices (ED) and their use in hybrid
technologies. Emerging devices are solid-state non-CMOS electronic devices, that are developed for
logic applications. There are many types of ED, the most well-known are certainly carbon nanotubes
(CNT) and single electron transistors (SET). Any 3-terminal electronic device that contains at least
one tunable potential barrier - to control carrier transport - is a potential post-CMOS device. Circuit
design also has to be completely re-evaluated in order to fit with specific device advantages and
limitations. All requirements (size, power consumption, speed,...) that ED should satisfy are listed in
the Section 1.5.1.
The biggest difference between CMOS technology and emerging technologies is probably the high
diversity of physical effects used to process logic information. For example, carrier transport laws in
carbon nanotubes, in single electron transistor and in spin-based transistors are completely different.
This results in a wider range of challenges to solve, in comparison with the highly mature and stable
CMOS technology. ED have focused attention for more than 20 years, and astonishingly the list of
devices is still long. The ideal post-CMOS device is for the moment not established. It might also
happen that no ED will beat future ultra-optimized nano-CMOS. What seems surer is that the types
and classes of ED will not increase. On the contrary, it is possible that R&D on some ED will slowly
stop. This is the price to pay for a lack of performances and reliability.
Furthermore, researchers studying ED are not guided by any equivalent Moore’s law 1 . As displayed
in Figure 1.24, the evolution from CMOS to emerging devices is difficult to be predicted.
Another specific difference between ED and CMOS is the quasi-independence of ED vs. scaling.
They are intrinsically nano-scale devices (carbon nanotubes) or can operate only at nano-size (SET).
Any type of equivalent Moore’s law on scaling for ED has no sense. Only performances comparison
is considered, and this is the goal set by the ITRS, in the Emerging Research Device section [Erd05].
A nice summary of emerging devices challenges and key points was proposed in 2005 by V. Zhirnov
[Zhi05]. A detailed review of semiconductors with and after CMOS was edited in 2005 by A.
Ionescu [Ion05].
Feature size
100μm
10μm
1μm
100nm
10nm
1nm
CMOS
CMOS IC evolution
Transition region
Quantum devices
Atomic dimensions
Emerging
devices
1960 1980 2000 2020 2040
Year
Figure 1.24: CMOS scaling and future emerging devices, adapted after J. D. Plummer [Plu01].
In terms of technology and fabrication process, all emerging devices essentially use the tools
developed for IC manufacturing. Even non-silicon-based devices (like CNT or molecular devices)
have an integration process based on surface micro-machining. Some specific fabrication facilities
have however been developed for ED, mainly in a bottom-up approach (AFM tips for carbon
nanotubes handling). Emerging devices classification, new materials developed and specific
integration tools are described in the next sections.
1. Engineers working on emerging devices navigate without a lighthouse! (comment by T. Skotnicki)
CMOS
Emerging
devices

34 CHAPTER 1: Introduction
Logic devices classification
Many types of micro-electronic devices have been proposed. Figure 1.25 follows from the ITRS
classification. The two main classes are CMOS (non-classical, evolutive, etc.) and alternative non-
CMOS devices. Inside these two families, different devices and geometries families are considered.
This classification needs of course to be re-evaluated at least once a year.
OTHER
DEVICES
ORGANIC
TRANSISTORS
FERROELECTRIC
TUNNEL FET
CMOS
NON-CLASSICAL
CMOS
OPTIMIZED
SCALING
SILICON ON
INSULATOR
FinFET
VERTICAL
MOSFET
DOUBLE GATE
TRI-GATE
GATE-ALL-
AROUND
Figure 1.25: Classification of micro-electronics devices. The two main families are CMOS and
quantum nanoelectronic devices.
1.5.1 What makes a logic family efficient?
CMOS technology is ideal for information processing. Any class of new devices should ideally
fulfill all the characteristics summarized below. Detailed references can be found in [Bec02],
[Was05] and [Llo00]. All ED have specific advantages and limitations. However, MOS devices (and
particularly nano-CMOS) still have the best characteristics.
1. Requirements for logic operations:
MICRO-ELECTRONIC
DEVICES FOR LOGIC
APPLICATION
EVOLUTIVE
CMOS
STRAINED
SILICON
SiGe
ULTRA-
SHALLOW
JUNCTIONS
HIGH-K
DIELECTRICS
METAL GATE
QUANTUM
NANOELECTRONIC
SOLID-STATE MACRO-MOLECULAR
NANOELECTRONIC DEVICES
COULOMB
BLOCKADE
DEVICES
SPINTRONICS
QUANTUM
CELLULAR
AUTOMATA
RESONANT
TUNNELING
DEVICES
FERROMAGNETIC
LOGIC
CARBON
NANOTUBES
MOLECULAR
DEVICES
DNA
CONDUCTION
• Non-linear characteristics:
A non-linear characteristic is required in logic gates, in order to maintain a high enough
signal-to-noise ratio. A strong non-linear system is less sensitive to noise and so the
distinction between ’’0’’ and ’’1’’ states is easier. The CMOS inverter is an example of a
non-linear operation obtained in CMOS technology.
• Power amplification:
Power amplification is necessary in order to maintain a sufficient signal level during logic
computing. Signal amplification also serve for noise rejection. In the case of digital
CMOS, amplification means both voltage and current amplification. Current amplification
is mandatory for FAN-OUT.
• Concatenability:
This means that input and output signal must be compatible. For example, if input is
electrical and output is optical, then transduction is mandatory. Neurologic computing use
for example both chemical and electrical signals.
• Feedback prevention:
The flow of operation must be in one direction.
• Complete set of boolean operators:
A minimum set of logic operations are necessary to build a logic system, for example OR
and AND gates, or NAND and NOR gates.

Technology hybridization with emerging devices 35
2. Parallelism at different hierarchical levels:
A high level of parallel operations is needed to have fast and efficient computation. Some
devices, like nanowires or nanotubes, have ideal intrinsic morphology for parallel and
matrix operations.
3. Emphasis on interconnect:
As the number of devices increases, interconnect management is getting more and more
complicated, and this problem should be clearly addressed.
4. Defect and fault tolerant:
Various circuits and systems design techniques have been proposed to have defect- and
fault-tolerant architectures. This is particularly important with nano-scale devices where
reliability is an issue [Sch04].
5. Architecture flexibility:
Circuits designers ask a lot of flexibility for many different types of applications.
6. Reliability:
CMOS technology has excellent reliability. Any technology based on emerging devices
should also demonstrate as good a reliability as possible.
7. Low power:
Device power dissipation has to be controlled. Many systems have limited access to power
supply systems (autonomous systems) and electronic components have to be protected
from over-heating resulting from power dissipation (supplied systems).
8. High speed:
The speed of an electronic system is directly dependent from the speed of the devices
used.
9. Small surface and volume:
The surface and the volume of integrated circuits should be as small as possible. A level of
integration of 10 9 devices per chip has recently been exceeded.
10. Room temperature operation:
This requirement is particularly important in single electronics, where the function of
devices at room temperature is a major issue. MOS devices are operational devices at
room temperature, even if their performances are better at low temperature (steeper subthreshold
slope and higher carrier mobility).
11. Modeling and physics:
CMOS is a mature technology, the physics of the MOS transistor is well described,
especially in long-channel devices where quantization effects are negligible. High-density
CMOS circuits are simulated in various commercial softwares. There is no chance for any
new or nano-scale devices to be integrated in any high-density circuits if the physics of the
device is not perfectly known, and if there are also no efficient simulation tools.
12. Cost, energy and environment:
There is no chance for any technology if the fabrication cost is not strictly controlled.
Investments for advanced integration facilities are huge, there are only a few companies
world-wide that can produce up-to-date IC. Any mistake in the choice of a technology
generation can freeze developments for many years.
Furthermore, considerations such as (i) energy power saving during fabrication, (ii) timeto-market
for new technology, (iii) impact on environment, (iv) material recycling and (v)
social fairness - are also crucial engineers responsibilities. ITRS has a roadmap for
environment, safety and health: [Esh06].

36 CHAPTER 1: Introduction
1.5.2 The single electron transistor
The single electron transistor (SET) is a three-contact electronic device, that fulfill a switch function
based on the phenomenon of Coulomb Blockade. An SET can theoretically control the transfer of a
few or even a single electron charge from source to island, and from island to drain. A single electron
transistor is made up with the following parts (see Figure 1.26):
• An island (the single electron box):
The island is the central quantum dot of the device. The island material needs to be
conductive. In theory, any metal or semiconductor can fit SET requirements, but in
practice, silicon is widely used. Furthermore, in order to be charge sensitive, the size of the
island should be as small as possible (a few nanometers), especially for room temperature
operation. In the literature, SET refers to mono-island single electron transistor. Multiple
island single electron devices are described in the Section 1.5.3.
• Drain and Source:
Drain and source are the two carrier reservoirs, like in a MOS transistor.
• Two tunnel junctions:
A big difference between MOSFET and SET is that MOSFET pn junctions are replaced
by tunnel junctions, between drain and island, and between island and source. These
junctions allow the blockade of charges in the island. Different ways to induce tunnel
junctions have been evaluated, the main ones are nano-constrictions and Fowler-
Nordheim tunneling through ultra-thin dielectric layers.
• A gate:
The gate is capacitively coupled to the island (capacitive SET) and controls the island bias
to turn ON/OFF the transistor. Double-gate, multiple-gate or GAA are also investigated.
I DS
Drain Source
Gate
Tunnel
junctions
Island
Figure 1.26: Conceptual 3D schematic of a mono-island single electron transistor.
In an SET, charge carriers are electrons. The concept of single hole transistor has also been proposed
and studied [Tan00]. The detailed physics of carrier transport in an SET, based on Orthodox Theory
formulation, is discussed in the next chapter.
Gate
C G
Drain
Source
C , R TD TD
Tunnel
Island
junctions
C TS , R TS
CTD : Drain tunnel junction capacitance
CTS : Source tunnel junction capacitance
CG : Gate capacitance
RTD : Drain tunnel junction resistance
RTS : Source tunnel junction resistance
Figure 1.27: The three terminals of a single electron transistor and associated parameters.
I DS

Technology hybridization with emerging devices 37
The two conditions to observe single electron characteristics are:
• Charging energy:
As the size of a single electron box decreases, then the energy required to add a single
excess charge to the dot increases. If the size is sufficiently small and if the charging
energy is much higher than the thermal energy, no electron can tunnel to and from the
quantum dot. Thus, the number of excess charges inside the island takes a discrete value.
This electrostatic effect that blocks charges in the island is called Coulomb Blockade
(CB). CB is observed in a single electron box only if the condition expressed by Equation
1.7 is fulfilled, where C Σ is the capacitance of the quantum dot (C Σ =C G +C TD +C TS ), k B
the Boltzmann constant and T the temperature of the system.
In an SET, the gate controls the potential of the island. If a positive bias is applied to the
gate, the tunneling probability from source to island increases and an extra electron can be
stored in the island, increasing the charging level of the island. If the gate voltage bias is
reduced, then this extra charging electron is released and the charging level inside the
island decreases. The current flow is thus controlled by a discrete charging-decharging
electrostatic transfer.
• Tunnel resistance:
In order to work properly, the tunnel junction resistance should be higher than the
quantum of resistance R Q =h/e 2 =26kΩ. This condition is a consequence of the application
of Heisenberg’s uncertainty principle. The product of the quantum dot charging energy
ΔW~e 2 /C Σ by the time constant of the charging through the tunnel junction Δt=R T C T has
to be higher than Planck’s constant h. This results in the condition given by Equation 1.8.
e 2
--------- > k
2C BT Σ
The direct consequence of Equation 1.7 is that SET are functional only at very low temperature or if
the capacitance C Σ is extremely small. If we consider a room temperature (RT=300K) operating
system, and a factor of 10 to get rid of thermoionic emission, then we can write the charging energy
as e 2 /2C Σ=10k BT, and finally we extract a quantum dot capacitance as small as 0.6aF!
The capacitance of a conductive spherical dot is calculated by using Equation 1.9, with ε the
permittivity and r the radius of the dot [Was01]. If we consider silicon dioxide as the dielectric
(ε=3.9ε 0), then we find that an island capacitance of 0.6aF corresponds to a radius as small as 1.4nm.
Thus, an island with a maximum diameter on the order of 1-2nm is needed for ambient operation.
About 1nm SET island diameter is needed for proper room temperature logic applications. The
maximum operating temperature at which a silicon island SET can properly work under Coulomb
Blockade is called the Kirihara’s criteria [Kir94] and is given by Equation 1.10.
C Σ
Operation of single electron transistors
(1.7) RT (1.8)
e 2
>
e
(1.9) (1.10)
2
If the size of the SET island and the temperature are small enough to meet Kirihara’s criteria, then
Coulomb Blockade characteristics are visible.
The plots in Figure 1.28 are Monte Carlo simulation of the I D -V G (left) and I D -V D (right)
characteristics of a single electron transistor. The I D -V G simulated curve shows typical Coulomb
Oscillations (CO) with a period equal to e/C G - corresponding to successive electrons charged in the
island.
The I D -V D simulation of a same device with same characteristics exhibits three regions: at low
negative and high positive V D bias, the characteristic is quasi-linear. Centered at around V D =0, there
is a conduction gap, called the Coulomb gap, with no current flow through the device.
---h
= 4πεr
Tmax =
---------------
40kCΣ

38 CHAPTER 1: Introduction
Detailed geometries and architectures of an SET transistor are given in the next chapter (Section 2.2),
and particularly the exact origin of tunnel barriers and quantum dot.
Drain Current, I D [nA]
35
30
25
20
15
10
period=e/C G
5
T=4.5K
0
T=100mK
0 25 50 75 100 125 150
Gate Voltage, V G [mV]
T=20K
Figure 1.28: Monte-Carlo (MC) I D -V G (V D =10mV) (left) and I D -V D (V G =50mV) (right) SET
simulation. Four different temperatures are set: 100mK, 4.5K (liquid helium temperature), 20K and
77K (liquid nitrogen temperature). Transistor characteristics are R S =R D =100kΩ, C S =C D =2aF,
C G =4aF. The simulation is calculated with SIMON [Was97] with 100’000 MC event numbers.
CB characteristics of a single electron transistor are efficiently plotted in a diamond diagram (see
Figure 1.29). Inside rhomboid shapes the different charging levels allowed in the island are written.
At low V D , the Coulomb gap is characterized by a device blockade (no current), and so the
transconductance g m =dI D /dV G is equal to zero. The transconductance sign is not considered.
50mV
V D [V]
0
-50mV
T=77K
Figure 1.29: Coulomb Blockade V D -V G diamond plot simulated at T=4.5K. Numbers enclosed are
possible electron charge levels in the island. Tunneling events through source tunnel junction
(J source ) and drain tunnel junction (J drain ) are represented. Parameters are those used in Figure 1.28.
Concerning the output characteristics of an SET, we observe:
Drain Current, I D [nA]
-200
-50 -25 0 25 50
• Double threshold level:
An SET has a double threshold level: in V G and V D . The V G threshold depends on
periodicity. The V D threshold is characterized by the Coulomb gap and is given by the
relation: -e/2C Σ

Technology hybridization with emerging devices 39
The island material is of crucial importance for device operation. To highlight this difference, the
impact on the density of state is represented in Figure 1.30. Three types of devices are compared:
SET, QDT and RTD.
The quantum dot transistor (QDT) is a single electron transistor with a semiconductor island. Now, it
is widely admitted to call SET devices with either a metallic or a semiconductor island.
Semiconductor-island SET have a different behavior in comparison with metallic-island SET. This is
due to quantum confinement and field effect in the island. Resonant Tunneling Devices (RTD)
physic is described in Section 1.5.4.
- SET -
Single Electron
Transistor
Figure 1.30: Impact of density of state and dimension [Gau03a].
Single electron transistor device and process simulation
Concerning SET modeling, many different approaches have been investigated. Carrier transport
from quantum dot to quantum dot through tunnel junctions under different bias conditions can be
efficiently solved with a Master Equation. This is a conservation law for all probabilities of states
that a circuit can occupy. This is also a common way of solving a stochastic process. Master Equation
can be solved directly, this is particularly well-adapted for a single-electron box or a single electron
transistor. Quasi-analytical models of SET have been proposed, first in 1992 by Ingold [Ing92], then
an excellent report was published in 1999 by Likharev [Lik99]. Latest contributions are focused on
hybrid CMOS/SET simulation [Mah06].
When the number of junctions and dots increases, then the Monte Carlo (MC) method is preferred.
MC is a computing method using random numbers and is efficient to simulate multiple stochastic
processes. The SIMON simulator [Was01] is one of the most efficient available simulator. Various
Monte Carlo contributions on SET simulation can be found in the literature; we can quote the works
of Roy in 1994 [Roy94], Fonseca in 1995, who called its tool SENECA [Fon95] and Chen, who
developed the simulator tool MOSES [Che96] in 1996.
Some groups have also recently extended the analytical simulation of SET into true 3-dimensional
simulation. This is essential to explore parameters like the different levels of quantum confinement
or the role of the quantum dot shape, doping and stress in semiconductor-based SET. The report
published by Fiori [Fio05] in 2005 is a pioneering work and is of high importance for prototyped
SET device optimization. SET simulation based on finite elements has also been explored [Hei02].
Finally, the fabrication process itself is also more and more focusing interest with the development of
full 3D finite-element simulators. Some key point fabrication steps, like stress induced by silicon
oxidation (PADOX), are very difficult to simulate in a full 3D configuration. Examples of TCAD
process and device simulations is presented in detail in Chapter 3.
Challenges of SET technology
e -
- Metallic island
- Sequential tunneling
- Coulomb Blockade
- R T >>R Q
e -
- QDT -
Quantum Dot
Transistor
E C EC
- Semiconductor island
- Sequential tunneling
- Coulomb Blockade
- Quantum confinement
- R T >>R Q
- RTD -
Resonant Tunneling
Device
SET challenges are enormous (See Section 2.2), due to the difficulty to isolate a 1 to 3nm-large
conductive box and to connect it through two resistive tunnel junctions. There is - for the moment -
no technique with SET reproducible characteristics. Other issues are the operating temperature
(ideally room temperature), the driving current, the gate integration, as well as the process cost.
A typical example presented in Figure 1.31 is an SET device based on SOI island point contact and
using a top polysilicon gate (left). Oscillating characteristics at different temperatures are also plotted
(right), showing the progressive disappearance of Coulomb Blockade at higher temperature [Sai02].
e -
Δ
- Semiconductor well
- Quantum confinement
- Resonant tunneling
- No Coulomb Blockade
- Phase coherent

40 CHAPTER 1: Introduction
Figure 1.31: SOI point contact SET (left) and I D -V G measurement (right) [Sai02].
Single electron history
In parallel to the CMOS history, a short history of Coulomb Blockade is given in Table 1.3. This
summaries a Century of research on electrostatic devices. This starts from the measurement of the
electron charge, in 1911, by R. Millikan; followed in 1951 by the Coulomb Blockade observation, by
C. Gorter; and finally first hybrid SET/CMOS integration in 2006, by the group of Yu and Choi.
TABLE 1.3: A BRIEF HISTORY OF COULOMB BLOCKADE PHYSICS AND DEVICES.
Year Group Study Reference
1911 Millikan Measurement of the electron charge [Mil11]
1924 de Broglie Basis of quantum mechanics [Bar01]
1951 Gorter Tunnel barriers in thin metallic films [Gor51]
1975
Kulik and
Shekhter
Basis of Orthodox Theory [Kul75]
1985 Averin and Likharev Orthodox Theory and quantum of resistance [Ave91]
1987 Fulton and Dolan
Demonstration of a single electron electrostatic trapping in
a conductive island between 2 junctions
[Ful87]
1987 Likharev Concept of electron trap and single electron logic [Lik87]
1990 Geerligs The electron turnstile [Gee90]
1991 Pothier The electron pump [Pot91]
1991 Averin and Likharev Description of the background charge effect [Ave91]
1993 Yano Realization of the first SEM cell [Yan93]
1995 Tiwari First nano-crystal memory [Tiw95]
1996 Takahashi Silicon SET by PADOX process [Tak96]
1998 Yano 128Mb SEM [Yan98]
2001 Wasshuber SET Monte Carlo modeling [Was01]
2001
Boeuf and
Monfray
Coulomb Blockade in nano-scale MOS devices
[Boe01]
[Mon03]
2001 Kim Electrically induced quantum dot [Kim01]
2002 Fraboulet Coulomb Blockade in SOI nano-constriction [Fra02]
2003 Nejo and Hori Coulomb Blockade in carbon nanotube [Nej03]
2004 Ionescu and Mahapatra
Hybrid SET/MOS architecture with CB oscillations and
high current drive
[Ion04]
2006 Lee and Yan Room temperature CB oscillations in Si SET [Lee06]
2006 Yu SET/MOSFET multiple-value SRAM circuit [Yu06]

Technology hybridization with emerging devices 41
1.5.3 Multiple-island single electron devices
The extremely high difficulty to process a device with a unique single island connected between two
tunnel junctions to carrier reservoirs has motivated researchers to develop single electron devices
with multiple islands. Multiple-island devices are much easier to fabricate. The nano-metric size of a
conductive dot can be naturally formed in a poly-crystalline material. The first observation of
Coulomb Blockade in thin metallic films by Gorter in 1951 [Gor51] was an example of electrostatic
charge trapping in a granular layer. Since then, many examples have been developed and transport
theory in poly-crystalline films is better understood. In this section, we present devices based on
metallic, poly-silicon and undulated SOI layers.
A single electron device - based on a metallic multiple-dot layer - was proposed in 1997 by [Che97].
The metal film contacted between two gold pads is made of 3nm diameter AuPd islands randomly
cross-connected by multiple tunnel junctions. Irregular I D -V G oscillations are observed up to T=77K.
A very recent report, published in 2005 by EPFL [Eco05a], exploits the unique transport
characteristics in low-doped ultra-thin LPCVD polysilicon nanowires (grain diameter ranging from 5
to 20nm), combined with MOS devices in a hybrid technology platform. Carriers transport through
polysilicon grains is explained by tunneling conduction at low temperature and hopping conduction
at higher temperature. The tunneling transport disappears at high temperature (T>80K) because the
potential barrier between the grains is not high enough in comparison with the thermal energy of
carriers. The current path from grain to grain is called percolation current. Authors have measured
hybrid CMOS/polysilicon nanowire basic configurations and have extracted a negative differential
resistance (NDR). Applications for pA-range current measurement and ultra-steep -10mV/dec NDR
characteristics with 8 decades peak-to-valley current ratio are suggested. A picture of the NMOS/
polysilicon nanowire cell is shown in Figure 1.37.
The work presented in 2002 by Kawamura [Kaw02] also exploits conduction in thin poly-silicon
layers and CB oscillations were observed up to 80K, with a tunnel barrier height between dots of
~26meV. A Coulomb gap in the I D-V D characteristic is also observed at low temperature on thinnest
reported polysilicon layers (7nm). The electrical characteristic of the device strongly depends on its
film thickness, channel width and length, film doping level and deposition technique. Authors also
demonstrate that small grains are needed for higher-temperature operational CB characteristics.
Figure 1.32: Single electron device based on
undulated ultra-thin SOI layer (top) and
measured oscillating I D-V G (down)
characteristics at T=20K and T=80K [Uch01].
The device presented in Figure 1.32 is proposed
by Uchida [Uch01]. The multi-island material is
an ultra-thin SOI layer, connected between two
thick SOI pads, serving as S/D contacts, and
controls by a deposited polysilicon gate. The
gate oxide is a 50nm grown SiO 2 layer.
The SOI thin film is attacked during the process
by an alkaline-based solution, resulting in a
3nm thick undulated silicon structure. AFM
measurement show a long range correlation
between Si grains of about 15nm.
As shown in the measurement plot, CB
oscillations are observed at low temperature.
A non-volatile memory hysteresis is also
observed in the I D -V G curve, even at T=300K.
The conduction between Si dots is explained by
the random potential profile in the film. Details
are in [Uch01].
CB oscillations and memory hysteresis are two
distinct effects and are discussed separately.

42 CHAPTER 1: Introduction
The latest work highlighted in this section dealing with multiple-island devices are memories
proposed by Yano’s group [Yan98]. In many multiple-island devices, including the work of [Eco05a]
and [Uch01], memory effects are observed. The storage mechanism in Yano’s memories is explained
by the trapping of charges in one or a few grains, that induce a modification in the percolation
channel conductance. Multiple-island memory applications are certainly more promising than logic
applications because they operate at room temperature and they do not depend on random CB
oscillations.
1.5.4 Resonant tunneling devices
As explained in section 1.5.1, logic devices need to exhibit a non-linear characteristic. The Resonant
Tunneling Device (RTD) logic family is based on resonant tunnel diodes combined with active
devices (MOS, BJT, HBT, HEMT) [Was05].
A resonant tunnel diode is a two-contact device with two junctions in series, as shown in Figure 1.33.
Structures are typically made of III-V semiconductors epitaxial layers and exhibit a negative
differential resistance in I-V characteristics. Wide-bandgap semiconductors are used as barriers. This
NDR effect results from resonance peaks in the transmission probability through the tunnel barriers.
A comparison between single electron devices and RTD is made in Figure 1.30.
3 10 -3
I DIODE [A]
High tunneling
probability
NDR
0
0 1.0
V DIODE [V]
Figure 1.33: Measured resonant tunneling
diode integrated on the VCO circuit presented
by [Cho06]. Diode surface is 2x1μm 2 .
Resonant tunneling diodes have many advantages in terms of reliability, ultra-high speed and power
consumption. On the other hand, limitations are resulting from the need to co-integrate active devices
to control diodes operation, and also from a complex and costly fabrication process requiring III-V
semiconductor epitaxial layers.
1.5.5 Carbon nanotubes
Tunnel
junctions
Low tunneling
probability
I D
Data processing with RTD coupled with
capacitors is presented in [Tan03]. This paper
explains the MOBILE (monostable-bistable
transition logic element) logic, that exploits
RTD NDR stability points. A delay between
logic gates as short as 100fs is demonstrated.
The second reference [Cho06] is a work of the
Korean KAIST group published in 2006.
Authors demonstrated the fabrication of a
14GHz monolithic microwave integrated circuit
voltage-controlled oscillator (VCO) with an
extremely reduced DC power consumption.
RTD used are based on InP - InGaAs multilayers
with different doping levels, and are
combined with HBT, varactors, spiral inductors
and thin-film resistors in an outstanding cointegration
of hybrid devices.
Carbon nanotubes (CNT) are promising nanostructures. A single-walled carbon nanotube (SWCNT)
is defined as a single graphite plane (so-called graphene) rolled up to a hollow seamless cylinder. A
multiple-walled carbon nanotube (MWCNT) is composed by multiple graphene sheets stuck into
another. The diameter of a CNT ranges from 1 to 10nm, while its length can be as long as tens of
micrometers. The discovery of CNT is attributed to Iijima [Iij91], in 1991.
In 2006, CNT are still reported as the hottest topic in nanotechnology by Nature [Top06], being the
device with super-strong mechanical properties and remarkable electronic characteristics. Let’s
notice that the same article put 1D nanowires (Section 1.5.6) in the second position.
Carbon nanotubes can be produced either in mass or assembled individually by local growth
[Was05]. However, the exact localization of CNT with ohmic contacts remains an unresolved
technological challenge. The first nanotubes produced by Iijima where synthesized by electric arc
discharge. This methods consists in applying a large voltage bias between two graphite electrodes.
Later, laser vaporization was introduced to enhance the yield of SWCNT (~70%). Chemical vapor
deposition of SWCNT was reported in 1998, and in 2001 the crystallization of fullerene structures.

Technology hybridization with emerging devices 43
The growth of individual CNT has the major advantage to control the position of one of the CNT
end. Many techniques are still investigated. They are almost all based on CVD catalytic growth from
a metal nanoparticle.
Detailed electronic properties of CNT can be found in [Was05]. Depending on carbon atoms
orientation (called chirality of the tube), SWCNT are either metallic or p-type semiconductor, with a
probability of 1/3 and 2/3, respectively. Semiconductor-type CNT have a bandgap of a few eV; the
bandgap decreases when the diameter of the tube increases. Due to CNT structures, authors expect
ballistic transport along the tube over distances of several micrometers. In longer CNT, phonon
scattering and scattering with doping impurities in the tube must be considered.
Figure 1.34 shows two realizations using carbon nanotubes. On the left, parallel CNT are used as
interconnect [Kre02] to take advantage of the high current density measured in metallic-type CNT
(~10 10 A/cm 2 for a CNT and ~10 7 A/cm 2 for copper). On the right, a SWCNT serves as the channel of
a CNT-based field effect transistor [Bac01]. The gate is below the tube and made of aluminium,
while two gold bonds serve as S/D contacts. For about ten years, CNT-FET with good performances
have been reported, for example by the IBM Watson Research Center [Col01], which uses electrical
breakdown to isolate a semiconductor-type SWCNT as a transistor channel.
In comparison with state-of-the-art silicon MOSFET, CNT-FET have a much higher ON-current.
However, major difficulties remain in the exact positioning of the tube, in the semiconductor nature
of the tube, in the doping control (n-type semiconductor CNT are difficult to be produced) and in the
metal/CNT contact (Schottky barriers are usually obtained). Furthermore, high-current CNT-FET
devices exploiting parallel connection of CNT have not been realized yet. The effect of the gate field
on short-channel CNT-FET has also not been clearly explored. Last, the reproducibility and yield of
CNT-FET technology is for the moment absolutely not under control.
2μm
100nm Al
Nanotube
CNT Interconnect CNT FET
Figure 1.34: Two applications of carbon nanotubes. On the left, a nanotube ball used as an
interconnect between two metal layers [Kre02]. On the right, the example of a field effect transistor
using a single SWCNT as channel of the device [Bac01].
Coulomb blockade oscillations in CNT nanostructures have also been observed. Using a CNT tip as
a field emitter, a Japanese group [Nej03] has measured I D -V G CB oscillations and I D -V D Coulomb
gap. CB peaks indicate the presence of defects in the CNT or at the contacts, that act as quantum dots
and tunnel barriers. The exact origin of quantum dots and tunnel barriers in CNT-based single
electron devices is still controversial. However, there is a lot of experimental work to do in order to
control the conduction in a CNT, despite the fact that many reports demonstrate the possible use of
CNT for room temperature CB operation.
The last example of CNT is their use in Nano Electro-Mechanical Systems (NEMS). CNT have
exceptional mechanical properties and a very high breaking resistance. A CNT electrostatic nanorelay
is presented in [Lee04b]. Authors exploit the small dimension and high stiffness of the tube to
actuate ON/OFF a relay at very high frequency and at low voltage.
Some outstanding results have been obtained with carbon nanotubes, and the range of possible
applications is really large. The fabrication of CNT-based field-effect transistors has been validated
during the last couple of years by many successful integrations. However, the lack of device-todevice
reliability and the low yield make the CNT technology at the moment far away to be a
possible option to replace CMOS logic.
Au

44 CHAPTER 1: Introduction
1.5.6 1D nanowires
One-dimensional nanowires are conductive structures with a uni-directional current flow. Carbon
nanotubes are specific 1D structures and have been discussed in the previous section. Although
nanowire materials are well-known (Si, SiGe, III-V compounds, metal), the nano-scale dimension,
1D quantum transport and surface/volume ratio make that nanowires exhibit very specific
characteristics. The ITRS is for a couple of years considering many types of 1D nanowires as
possible post-CMOS devices for logic applications. However, the range of applications for 1D
nanowires is very large, including sensors, actuators and optical applications.
The term nanowire appears for the first time in the literature in 1991. It was introduced by Knoedler
in a study on GaAs/AlGaAs heterostructures [Kno91]. Since then, many different technological
approaches have been considered, including both bottom-up and top-down fabrication processes.
Conduction in gold nanowires has been published by [Tak01]. The Harvard group of Lieber has
pushed a lot of effort on various nanowire studies. This includes the synthesis of semiconductor
compound nanowires (GaAs, GaP, InP) [Dua00] and crystalline cadmium sulfide (CdS) nanowire
lasers [Dua03]. In 2003, Heath’s group from Caltech [Mel03] has emphasized the possibility to build
ultra-high-density nanowires for circuits applications. As small of 8nm-diameter nanowires have
been placed in a regular array structure with a pitch of only 16nm, demonstrating a nanowire junction
density of 10 11 cm -2 for cross-bar circuit applications.
Many reports are also published on silicon nanowires (SiNW). As the main part of this thesis report
is on SET/FET properties in silicon nanowires, we are not going to describe here in detail the
electronic properties and all proposed SiNW integration possibilities. As an introduction, we rather
show some key results.
The paper on SiNW atomistic simulation published by Lannoo’s group at ESSDERC 2005 [Neh05] is
a highly remarkable introduction on SiNW transport computation. An example of a 9nm long and
1.36nm x 1.36nm cross-section SiNW is shown, and influence of SiNW length and width in the
ballistic regime is highlighted. In terms of technology and devices, an original top-down approach
using crystal-orientation-dependent silicon etching was proposed in 1997 by NTT [Nam97]. Authors
obtained 2nm-width SiNW, showing oscillations at low temperature. In 2005, the CEA Grenoble
group has measured CB oscillations in a SiNW MOSFET configuration [Hof05]. The role of single
local traps, their natures and positions in the channel is explained. Measurements of regular low
temperature I D-V G oscillations are shown and the parasitic background charge effect in SiNW single
electron devices is, for the first time, addressed.
10nm
Figure 1.35: The nanowire FET architecture
proposed by Lieber (top) and a Ge/Si nanowire
cross-section TEM image (bottom). ZrO 2 is
used as gate oxide and Au as top gate [Xia06].
Finally, the last two contributions that deserve a
special attention are: first, a paper published in
2006 by Lieber’s group [Xia06]. The structure
of the nanowire device and a device crosssection
are displayed in Figure 1.35. A dual Ge/
Si nanowire core is used, combined with high-k
dielectrics and a Au gate. Extracted p-type
nanowire FET I ON is 2.1mA/μm. The shell Si/
Ge structure is not small enough to exhibit 1D
confined conduction, but reduced scattering due
to low wire doping, excellent S/D contacts and
ballisticity at low V D are observed.
The second remarkable SiNW FET paper
reported in 2006 was published by [Par06] is a
twin silicon-nanowire transistor in a gate-allaround
configuration. A n-channel silicon
device, 10nm in diameter, with 30nm gate
length has been characterized. The gate oxide
thickness is 2nm and compound TiN/W is used
as gate material. I ON is 3.5mA/μm and I OFF is
13nA/μm. The short channel immunity is
excellent.

Technology hybridization with emerging devices 45
1.5.7 Macro-molecular devices
Macro-molecular devices exploit specific transport characteristics through organic molecules. Some
macro-molecules, inc. carbon nanotubes, have electrical switching properties that make them
valuable for computational electronics. The bistable characteristic of molecules can be observed in
terms of (i) molecule electronic excitation and Coulomb blockade, (ii) in the molecule configuration
or conformation change or (iii) in a reversible redox process. The nature of switching and the
electronic structures of macro-molecules is a brand new field of interest. Many types of macromolecules
have been investigated, including also the biologic DNA molecule.
In terms of device performances and technology integration, this class of devices has essentially the
same advantages and limitations than carbon nanotubes:
• Contacts:
It is an enormous challenge to control the contact and position of a single molecule or a
few molecules between two electrodes acting as drain and source. A third electrode in the
boundary of the molecular system is needed to control the conduction through the
molecular system. The reliability of ultra-sharp metallic electrodes can also provide
instabilities.
• Chemical synthesis:
The molecules are chemically synthesized and then deposited during the process over the
surface of the wafer. The thermal balance and material compatibility is usually more
critical than in CMOS technology. A general description is hardly possible and organic
molecules (rotaxanes, catenanes) have many types of electrical behavior (conductive,
insulator, semiconductor).
• Reproducibility:
A single molecule has a perfectly defined and reproducible electrical behavior. However,
due to contacting, molecule position and molecule ageing (oxidation), a good device-todevice
reproducibility cannot still be achieved. Furthermore, any misalignment in the
molecule position or any defective single bond can completely change the property of the
device. A defect-tolerant circuit approach is often considered to counter the poor
reproducibility and non-working devices.
• Device performances:
Because of the nano-scale of a single molecule, ITRS expects advantages in devices speed
(>THz), low switching energy and ultra-high density (>10 12 cm -2 ).
• Bottom-up:
Molecular devices are intrinsically integrated in a bottom-up approach.
A large range of device architectures and functions have been experimentally proposed and
measured. Two-contact devices are molecular wires, diodes, switches, storage elements and
interconnects. Three-terminal devices include either molecules contacted by three leads or transistor
configurations where a third gate electrode modifies the molecule conductivity by field effect.
In 1998, Hewlett-Packard has proposed the Teramac concept [Hea98], which consists in building
large arrays of cross-bar components to study how defects affect the general circuit operation.
Teramac concept proposes nice ideas for the future of nano-electronics and nano-components. Many
reports are also focusing on specific types of molecules. For example, in 1999, a partnership between
Yale and Rice universities [Che99] presented a redox two-terminal molecular-based device
exhibiting negative differential resistance and an I ON/I OFF ratio greater than 1000. One year later, in
2000, the conduction through a single DNA molecule was characterized [Por00], exhibiting a
semiconducting behavior.
More recent articles include contributions on electrode fabrication by controlled breakdown
junctions [Rei02] and the observation of Coulomb blockade and Kondo effect in a three-terminal
single molecule transistor [Par02]. Finally, in 2006, a group from North Carolina State University
[Gow06] published an hybridization of CMOS devices with redox molecules. The molecule discrete
states manifest themselves in the transistor characteristics. This example shows that macromolecules
can be used in a huge number of applications, and usually at moderate cost. As for CNT,
contacts and reliability are the major issues that need to be solved.

46 CHAPTER 1: Introduction
1.5.8 Spintronics
Besides an electric charge, electrons are also characterized by a spin orientation. This is a
fundamental property, that can be exploited in computational nanoelectronics. For about 20 years, the
use of magnetoelectronic properties for data processing and storage has been investigated. In 1989,
Datta and Das have proposed a theoretical study on spin-polarized current flow in a 2D electron gas
[Dat89]. Novel activities on spintronics have followed then. We can summarize the basic operations
of a spin transistor in this way:
• Spin-oriented carrier generation from the source (ferromagnetic material)
• Flow of spin-polarized electrons through the channel (2D electron gas)
• Spin detection in the drain (ferromagnetic material)
If turned ON, the coupled gate flips the carrier spin by the external applied field and hence modify
the spin orientation. Random spin misalignment results in an increase in carrier scattering, and hence
an increase in the channel resistance. Otherwise, if no gate bias is applied, the channel should as
much as possible preserve spin orientation all along the charge transfer from source to drain.
Recently, various device architectures of spin-based transistors have been proposed: the spin gain
transistor [Nik05], the spin-torque concept [Bau03] and a spin MOSFET with spin-polarized
transport in silicon [Sug04].
However, spintronics is facing non-negligible issues. First, the injection of a spin domain in
semiconductor and control of this spin-relevant domain at small scale and for a significant time has
not been yet demonstrated. Second, the fabrication process involves both ferromagnetic materials
(Cr, Fe or Mn alloys) and III-V semiconductors for 2D electron-gas formation. Let’s notice finally,
that spintronics is still based on charge transfer and so performances may not highly differ from
electrical charge transport.
1.5.9 Ferromagnetic logic
Ferromagnetic devices are also spin-based devices and exploit the electron magnetic moment to store
and carry information. Contrary to spintronics, ferromagnetic logic consists in changing the magnetic
polarization of a metal (no semiconductors), and not carrying spin-oriented carriers from one
electrode to another (like spintronics).
For example, the work proposed by [All02] exploits a magnetic feedback loop for NOT gate and
shift register applications. The two stable states (spin up / spin down) of a ferromagnetic structure
represent the two logic states (0 / 1). A second example proposed by the London University College
[Par03] is called bistable magnetic quantum cellular automata (BMQCA). This device is based on
single magnetic dots placed close together. The magnetic momentum of each magnetic quantum dot
can flip up and down, and this results in spin-orientation transfer through wires. Logic operations are
made with specific geometric configurations.
As in spintronics, the lack of demonstrator devices slows down the actual interest on ferromagnetic
logic. Furthermore, the information flow direction is not controlled in ferromagnetic systems.
Despite an expected ultra-low power consumption, large process difficulties for high-speed and highdensity
ferromagnetic arrays are inevitably limiting investments. Research activities are still
dominated by academic groups, and not by industries.
1.5.10 Devices comparison
The main families of devices for logic applications has been presented in the previous sections. A
stronger emphasis has been deliberately put on single electron devices and 1D nanowires. Monoisland
SET have also been described in more detail because of their higher relevance for this work.
The ITRS, in its latest release on emerging devices [Erd05], makes an in-depth comparison of
advantages and limitations of new devices, with CMOS as a reference. The Table 1.4 is a summary
of this comparison. This includes only main results.
Contrary to the CMOS technology, there is no Moore’s law on emerging devices. There is almost no
improvement linked with device scaling, and so device size is not considered in the Table.

Technology hybridization with emerging devices 47
TABLE 1.4: ITRS TABLE OF COMPARISON FOR EMERGING DEVICES - RELEASE 2005 [ERD05].
Device FET
1D
structures
Type Si CMOS CNT-FET
NW-FET
Cell size
(spatial pitch)
Density
(device/cm 2 )
Switch speed
Circuit speed
Switching
energy (J)
Bin. throughput
GBit/(ns.cm 2 )
Operational
temperature
1.5.11 Circuits and systems hybridization
Resonant
Tunnel
Devices
Mono-
Poly-
SET
It seems realistic that emerging devices will be progressively combined with CMOS in hybrid
technologies. No ED can - for the moment - exceed all advantages of a boosted CMOS technology;
but smart devices combination have still been demonstrated for some key applications.
Major advantages/drawbacks of SET/MOS devices are shown in Table 1.5. Advantages of a hybrid
CMOS-SET technology, including hybrid cells simulation can be found in [Mah06].
TABLE 1.5: MOSFET-SET DEVICES COMPARISON.
Molecular
RTD SET Molecular
Spin
transistor
Spin
transistors
100nm 100nm 100nm 40nm 10nm 100nm
590nm 1.5μm 3μm 700nm 2μm 100μm
10 10
Materials Si
Advantages
Limitations
4.5x10 9
4.5x10 9
6x10 10
10 12
4.5x10 9
2.8x10 8 4x10 7 10 7 2x10 8 2x10 7 10 4
12THz 6.3THz 16THz 10THz 1THz 40GHz
1THz 200MHz 700GHz 2THz 100Hz not known
61GHz 61GHz 61GHz 1GHz 1GHz not known
5.6GHz 220Hz 10GHz 1MHz 100Hz not known
3x10 -18 3x10 -18 3x10 -18 10 -18 5x10 -17 3x10 -18
10 -16 10 -11 10 -13 8x10 -17 3x10 -7 not known
238 238 238 10 1000 not known
1.6 10 -8 0.1 2x10 -4
2x10 -9 not known
RT RT 4.2-300K 20K RT RT
CNT, Si,
Ge, III-V
III-V,
SiGe
III-V, Si
Organic
molecules
Projected Demonstrated
MOSFET SET
High speed and fan-out
Mature and stable technology
Reasonably costly
SCE/DIBL
Power dissipation
Process variations at nano-scale
NMOS and PMOS devices
Nano-scale device
Ultra low power dissipation
Functions (oscillating)
Memory and logic device
Technology for RT operation
Reproducibility at nano-scale
High output impedance (~nA)
Background charge effects
Limited to low V D bias for CB
Low voltage gain C G/C S
Si, III-V,
Ferro

48 CHAPTER 1: Introduction
Many hybrid technologies can be found in the literature. The example proposed in Figure 1.36 was
proposed by EPFL in 2004. The complete reference, including the hybrid SET/MOS simulation used
is presented in [Ion04].
V DS1
I BIAS
SET
I DS1
GND
I IN
V
V GS2
GS1
V IN
I DS2
NMOS
V BIAS
V DS2
Log IDS2
VGS1 = VIN
Figure 1.36: Example of a hybrid SET-MOS basic cell (left) [Ion04]. The advantage of this
configuration is to offer a high output current with the cross-connected MOS buffer output. The
operating principle of this cell is presented on the right. The oscillating CB SET characteristics are
amplified by the MOS biased in weak inversion, resulting in a typical μA-range I IN current level.
Another MOS - single electron technology hybridization was also proposed by EPFL in 2005. Fully
characterized polysilicon multi-island wires combined with planar bulk MOS transistors are
described in [Eco05a] and [Eco05b] (see Section 1.5.3).
N-MOSFET Poly-Si NW FET
D
G
G
D S
S
Figure 1.37: SEM picture of a hybrid co-integration of a n-type MOSFET and a polysilicon
nanowire FET integrated on the same substrate (left). Zoom on the central core of the active
polysilicon nano-grain wire (right). The width of the channel is 312nm.
VDS1
IDS1
VIN = VGS1
VDS2 = (VIN−VBIAS)
VGS2 = (VDS1−VBIAS)
IIN
VDS1
VIN
I DS
VDS1
Log IDS2
312nm
IBIAS
VIN = VGS1
VDS2 = (VIN−VBIAS)
VGS2 = (VDS1−VBIAS)
Nano-grain
polysilicon

Summary 49
1.6 Summary
In this first chapter, we have presented different emerging devices combined with MOS transistors on
a same substrate. As an outstanding reference, the paper published by the Korean KAIST group on a
14GHz InP-Based RTD VCO with ultra-low-power consumption [Cho06] is, for example, a highly
valuable hybrid integration (see Section 1.5.4).
Hybridization is certainly mandatory for a smooth transition from CMOS technology to advanced
technology exploiting emerging devices. However, the co-integration is not a scope by itself, but
either a way to integrate new features, like ultra-low power logic or memory, which are impossible to
build only upon CMOS. The CMOS technology will stay dominant for high speed and performances,
and also as interface with external word.
The positioning of the three domains More Moore (Section 1.3), Beyond CMOS (Section 1.4) and
More than Moore (Section 1.5) are plotted in Figure 1.38.
Feature size
Figure 1.38: The positioning of More Moore, Beyond CMOS and More than Moore domains in terms
of scaling and evolution perspectives.
1.6.1 Synopsis
10μm
1μm
100nm
10nm
We proposed the following in this chapter:
More Moore
Beyond CMOS
1nm
1960 1980 2000 2020 2040 2060
Years
More than Moore
Micromechanics
High-voltage
Radio-Frequency
• Discussion on past and actual challenges in the semiconductor industry.
• The EPFL vision, based on an hybrid CMOS/SET co-integration, is shortly presented
and motivated.
• After a brief MOS device description and a short CMOS history, the device scaling based
on Dennard’s rules is introduced.
• The Moore’s law of scaling is discussed (More Moore).
• Problems and proposed solutions of actual nano-scale CMOS are explained.
• Tri-dimensional MOSFET structures are introduced as a beyond CMOS solution,
including the key gate-all-around geometry.
• The last part of this chapter is on emerging devices (More than Moore), with a specific
focus on single electron devices. Basic physics of the SET, based on the Coulomb
Blockade phenomenon, is explained. The performances of non-CMOS devices are also
compared.

50 CHAPTER 1: Introduction
1.7 Bibliography
[Ali00] J. Alieu, T. Skotnicki, E. Josse, J.-L. Regolini and G. Bremond, ’’Multiple SiGe well: a new channel
architecture for improving both NMOS and PMOS performances’’, Proceedings of VLSI Symposium
on Technology, pp. 130-131, Honolulu HI, 2000.
[All02] D. A. Allwood, G. Xiong, M. D. Cooke, C. C. Faulkner, D. Atkinson, N. Vernier and R. P. Cowburn,
’’Submicrometer ferromagnetic NOT gate and shift register’’, Science, vol. 296, pp. 2003-2006,
2002.
[Asa97] A. Asai and Y. Wada, ’’Technology challenges for integration near and below 0.1μm’’, Proceedings
of the IEEE, vol. 85 (4), pp. 505-520, 1997.
[Ase03] A. Asenov, A. R. Brown, J. H. Davies, S. Kaya and G. Slavcheva, ’’Simulation of intrinsic parameter
fluctuations in decananometer and nanometer-scale MOSFETs’’, IEEE Transactions on Electron
Devices, vol. 50 (9), pp. 1837-1852, 2003.
[Aug83] S. Augarten, ’’State of the art: a photographic history of the integrated circuit’’, Ticknor & Fields,
New-York NY, 1983.
[Ave91] D. V. Averin and K. K. Likharev, ’’Single-electronics: Correlated transfer of single electrons and
Cooper pairs in small tunnel junctions’’, Mesoscopic Phenomena in Solids, Elsevier Amsterdam NL,
pp. 173-271, 1991.
[Bac01] A. Bachtold, P. Hadley, T. Nakanishi and C. Dekker, ’’Logic circuits with carbon nanotube
transistors’’, Science, vol. 294, pp. 1317-1320, 2001.
[Bar48] J. Bardeen and W. H. Brattain, ’’The transistor, a semi-conductor triode’’, Physical Review, vol. 74,
pp. 230-231, 1948.
[Bar01] K. Barnham and D. Vvedensky, ’’Low-dimensional semiconductor structures’’, Cambridge
University Press, Cambridge UK, 2001.
[Bat07] E. Batail, S. Monfray, D. Rideau, M. Szczap, N. Loubet, T. Skotnicki, C. Tabone, J.-M. Hartmann, S.
Borel, G. Rabille, J.-M. Damlencourt, B. Vincent, B. Previtali, L. Clavelier, M. Bescond and G.
Ghibaudo, ’’Germanium-on-Nothing (GeON): an innovative technology for ultrathin Ge film
integration’’, Proceedings of ESSDERC, pp. 450-453, Munich DE, 2007.
[Bau03] G. E. W. Bauer, A. Brataas, Y. Tserkovnyak and B. J. van Wees, ’’Spin-torque transistor’’, Applied
Physics Letters, vol. 82 (22), pp. 3928-3930, 2003.
[Bec02] P. Beckett and A. Jennings, ’’Towards nanocomputer architecture’’, Proceedings of Asia-Pacific
Computer Systems Architecture, Melbourne AU, 2002.
[Bhu05] K. K. Bhuwalka, J. Schulze and I. Eisele, ’’Scaling the vertical tunnel FET with tunnel bandgap
modulation and gate workfunction engineering’’, IEEE Transactions on Electron Devices, vol. 52
(5), pp. 909-917, 2005.
[Boe01] F. Boeuf, T. Skotnicki, S. Monfray, C. Julien, D. Dutartre, J. Martins, P. Mazoyer, R. Palla, B. Tavel,
P. Ribot, E. Sondergard and M. Sanquer, ’’16 nm planar NMOSFET manufacturable within state-ofthe-art
CMOS process thanks to specific design and optimisation’’, Technical Digest of IEDM, pp.
29.5.1-29.5.4, Washington DC, 2001.
[Cha03] L. Chang, Y.-K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu and T.-J. King, ’’Extremely
scaled silicon nano-CMOS devices’’, Proceedings of the IEEE, vol. 91 (11), pp. 1860-1873, 2003.
[Che96] R. H. Chen, A. N. Korotkov and K. Likharev, ’’Single-electron transistor logic’’, Applied Physics
Letters, vol. 68 (14), pp. 1954-1956, 1996.
[Che97] W. Chen and H. Ahmed, ’’Metal-based single electron transistors’’, Journal of Vacuum Science and
Technology B, vol. 15 (4), pp. 1402-1405, 1997.
[Che99] J. Chen, M. A. Reed, A. M. Rawlett and J. M. Tour, ’’Large On-Off ratios and negative differential
resistance in a molecular electronic device’’, Science, vol. 286, pp. 1550-1552, 1999.
[Che04a] P. S. Chen, S. W. Lee, M. H. Lee, C. W. Liu and M. J. Tsai, ’’Thin relaxed SiGe layers for strained Si
CMOS’’, Proceedings of Semiconductor Manufacturing Technology Workshop, pp. 79-82, Taiwan
TW, 2004.
[Che04b] K. W. Chew, K. S. Yeo and S.-F. Chu, ’’Effect of technology scaling on the 1/f noise of deep
submicron PMOS transistors’’, Solid-State Electronics, vol. 48, pp. 1101-1109, 2004.
[Chi06] P. R. Chidambaram, C. Bowen, S. Chakravarthi, C. Machala and R. Wise, ’’Fundamentals of silicon
material properties for successful exploitation of strain engineering in modern CMOS
manufacturing’’, IEEE Transactions on Electron Devices, vol. 53 (5), pp. 944-964, 2006.

Bibliography 51
[Cho05] S. Chou, ’’Integration and innovation in the nanoelectronics era’’, Digest of Technical Papers of
ISSCC, vol. 1, pp. 36-41, 2005.
[Cho06] S. Choi, Y. Jeong and K. Yang, ’’14 GHz InP-based RTD MMIC VCOs with ultra low DC power
consumption’’, Proceedings of Indium Phosphide and Related Materials Conference, pp. 439-441,
Princeton NJ, 2006.
[Coc99] T. Cochet, S. Skotnicki, G. Ghibaudo and A. Poncet, ’’Lateral dependence of dopant-number
threshold voltage fluctuations in MOSFETs’’, Proceedings of ESSDERC, vol. 1, pp. 680-683,
Leuven BE, 1999.
[Col90] J.-P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes and C. Claeys, ’’Silicon-on-insulator
gate-all-around device’’, Technical Digest of IEDM, pp. 595-598, San Francisco CA, 1990.
[Col01] P. G. Collins, M. S. Arnold and P. Avouris, ’’Engineering carbon nanotubes and nanotube circuits
using electrical breakdown’’, Science, vol. 292, pp. 706-709, 2001.
[Dat89] S. Datta and B. Das, ’’Electronic analog of the electro-optic modulator’’, Applied Physics Letters,
vol. 56 (7), pp. 665-667, 1989.
[Dat02] S. Datta, ’’The non-equilibrium Green's function (NEGF) formalism: An elementary introduction’’,
Technical Digest of IEDM, pp. 703-706, San Francisco CA, 2002.
[Del00] S. Deleonibus, C. Caillat, G. Guegan, M. Heitzmann, M. E. Nier, S. Tedesco, B. Dal’zotto, F. Martin,
P. Mur, A. M. Papon, G. Le Carval, S. Biswas and D. Souil, ’’A 20-nm physical gate length
NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets’’,
IEEE Electron Device Letters, vol. 21 (4), pp. 173-175, 2000.
[Den07] R. H. Dennard, J. Cai and A. Kumar, ’’A perspective on today’s scaling challenges and possible
future directions’’ Solid-State Electronics, vol. 51 (4), pp. 518-525, 2007.
[Den74] R. H. Dennard, F. H. Gaensslen, H-N. Yu, V. L. Rideout, E. Bassous, A. R. Leblanc, ’’Design of ionimplanted
MOSFET's with very small physical dimensions’’, IEEE Journal of Solid-State Circuits,
vol. 9 (5), pp. 256-268, 1974.
[Dor02] B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R. A. Roy, O. Dokumaci, Z. Ren, J. Fen-Fen, S. Leathen,
W. Natzle, H-J. Huang, J. Mezzapelle, A. Mocuta, S. Womack, M. Gribelyuk, E. C. Jones, R. J.
Miller, H.-S. P. Wong and W. Haensch, ’’Extreme scaling with ultra-thin Si channel MOSFETs’’,
Technical Digest of IEDM, pp. 267-270, San Francisco CA, 2002.
[Dor03] B. Doris, M. Ieong, T. Zhu, Y. Zhang, M. Steen, W. Natzle, S. Callegari, V. Narayanan, J. Cai, S. H.
Ku, P. Jamison, Y. Li, Z. Ren, V. Ku, T. Boyd, T. Kanarsky, C. D'Emic, M. Newport, D. Dobuzinsky,
S. Deshpande, J. Petrus, R. Jammy and W. Haensch, ’’Device design considerations for ultra-thin
SOI MOSFETs’’, Technical Digest of IEDM, pp. 27.3.1-27.3.4, Washington DC, 2003.
[Doy03] B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios,
and R. Chau, ’’High performance fully-depleted tri-gate CMOS transistors’’, IEEE Electron Device
Letters, vol. 24 (4), pp. 263-265, 2003.
[Dua00] X. Duan and C. M. Lieber, ’’General synthesis of compound semiconductor nanowires’’, Advanced
Materials, vol. 12 (4), pp. 298-302, 2000.
[Dua03] X. Duan, Y. Huang, R. Agarwal and C. M. Lieber, ’’Single-nanowire electrically driven lasers’’,
Nature, vol. 421, pp. 241-245, 2003.
[Eco05a] S. Ecoffey, V. Pott, D. Bouvet, M. Mazza, S. Mahapatra, A. Schmid, Y. Leblebici, M. Declercq and
A. M. Ionescu, ’’Nano-wires for room temperature operated hybrid CMOS-NANO integrated
circuits’’, Digest of Technical Papers of ISSCC, pp. 260-262, San Francisco CA, 2005.
[Eco05b] S. Ecoffey, M. Mazza, V. Pott, D. Bouvet, A. Schmid, Y. Leblebici, M. Declercq and A. M. Ionescu,
’’A new logic family based on hybrid MOSFET-polysilicon nanowires’’, Technical Digest of IEDM,
pp. 269-272, Washington DC, 2005.
[Erd05] The International Roadmap for Semiconductor, ’’Emerging Research Device’’, 2005 Edition,
available at http://www.itrs.net/, 2005.
[Ern06] T. Ernst, F. Andrieu, O. Weber, C. Dupre, O. Faynot, F. Ducroquet, L. Clavelier, J.-M. Hartmann, S.
Barraud, G. Ghibaudo and S. Deleonibus, ’’High mobility nano-scaled CMOS: some opportunities
and challenges’’, Proceedings of ISTDM, pp. 1-2, Princeton NJ, 2006.
[Esh06] The International Roadmap for Semiconductor, ’’Environment, Safety and Health’’, 2006 Edition,
available at http://www.itrs.net/, 2006.
[Fen03] C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere and F. Boeuf, ’’Requirements for
ultra-thin-film devices and new materials on CMOS roadmap’’, IEEE International SOI Conference,
pp. 145-146, Newport Beach CA, 2003.

52 CHAPTER 1: Introduction
[Fio05] G. Fiori, M. G. Pala and G. Iannaccone, ’’Three-dimensional simulation of realistic single electron
transistors’’, IEEE Transactions on Nanotechnology, vol. 4 (4), pp. 415-421, 2005.
[Fon95] L. R. C. Fonseca, A. N. Korotkov, K. K. Likharev and A. A. Odintsov, ’’A numerical study of the
dynamics and statistics of single electron systems’’, Journal of Applied Physics, vol. 78 (5), pp.
3238-3251, 1995.
[Fos02] J. G. Fossum, L. Ge and M.-H. Chiang, ’’Speed superiority of scaled double-gate CMOS’’, IEEE
Transactions on Electron Devices, vol. 49 (5), pp. 808-811, 2002.
[Fra01] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur and H.-S. P. Wong, ’’Device scaling
limits of Si MOSFETs and their application dependencies’’, Proceedings of the IEEE, vol. 89 (3),
pp. 259-288, 2001.
[Fra02] D. Fraboulet, X. Jehl, D. Mariolle, C. Le Royer, G. Le Carval, P. Scheiblin, P. Rivallin, D.
Deleruyelle, L. Mollard, M. E. Nier, A. Toffoli, G. Molas, B. De Salvo, S. Deleonibus and M.
Sanquer, ’’Coulomb Blockade in thin SOI nanodevices’’, Proceedings of ESSDERC, pp. 395-398,
Bologna IT, 2002.
[Ful87] T. A. Fulton and G. D. Dolan, ’’Observation of single-electron charging effects in small tunnel
junctions’’, Physical Review Letters, vol. 59, pp. 109-112, 1987.
[Gau03a] J. Gautier, ’’Few electron electronics’’, EPFL lecture, 2003.
[Gau03b] J. Gautier, ’’Physique des dispositifs pour circuits intégrés silicium’’, Traité EGEM, Electronique et
micro-électronique, Editions Hermes FR, 2003.
[Gee90] L. J. Geerligs, V. F. Anderegg, P. A. M. Holweg and J. E. Mooij, ’’Frequency-locked turnstile device
for single electrons’’, Physical Review Letters, vol. 64, pp. 2691-2694, 1990.
[Gor51] C. J. Gorter, ’’A possible explanation of the increase of the electrical resistance of thin metal films at
low temperatures and small field strengths’’, Physica, vol. 17, 1951.
[Gow06] S. Gowda, G. Mathur, Q. Li, S. Surthi and V. Misra, ’’Hybrid silicon/molecular FETs: a study of the
interaction of redox-active molecules with silicon MOSFETs’’, IEEE Transactions on
Nanotechnology, vol. 5 (3), pp. 258-264, 2006.
[Gwo02] R. Gwoziecki and T. Skotnicki, ’’Physics of the subthreshold slope - Initial improvement and final
degradation in short CMOS devices’’, Proceedings of ESSDERC, pp. 639-642, Bologna IT, 2002.
[He06] R. He and P. Yang, ’’Giant piezoresistance effect in silicon nanowires’’, Nature nanotechnology, vol.
1, pp. 42-46, 2006.
[Hea98] J. R. Heath, P. J. Kuekes, G. S. Snider and R. S. Williams, ’’A defect-tolerant computer architecture:
opportunities for nanotechnology’’, Science, vol. 280, pp. 1716-1721, 1998.
[Hei02] F. O. Heinz, A. Schenk, A. Scholze and W. Fichtner, ’’Full quantum simulation of silicon-oninsulator
single-electron devices’’, Journal of Computational Electronics, vol. 1 (1), pp.161-164,
2002.
[Her01] J. M. Hergenrother, G. D. Wilk, T. Nigam, F. P. Klemens, D. Monroe, P. J. Silverman, T. W. Sorsch,
B. Busch, M. L. Green, M. R. Baker, T. Boone, M. K. Bude, N. A. Ciampa, E. J. Ferry, A. T. Fiory,
S. J. Hillenius, D. C. Jacobson, R. W. Johnson, P. Kalavade, R. Keller, C. A. King, A. Kornblit, H.
W. Krautter, J. T.-C. Lee, W. M. Mansfield, J. F. Miner, M. D. Morris, S.-H. Oh, J. M. Rosamilia, B.
J. Sapjeta, K. Short, K. Steiner, D. A. Muller, P. M. Voyles, J. L. Grazul, E. Shero, M. E. Givens, C.
Pomarede, M. Mazanec, and C. Werkhoven, ’’50 nm vertical replacement-gate (VRG) nMOSFETs
with ALD HfO2 and Al2O3 gate dielectrics’’, Technical Digest of IEDM, pp. 3.1.1-3.1.4,
Washington DC, 2001.
[Hof05] M. Hofheinz, X. Jehl, M. Sanquer, G. Molas, M. Vinet and S. Deleonibus, ’’Detection of individual
traps in silicon nanowire transistors’’, Proceedings of ESSDERC, pp. 225-228, Grenoble FR, 2005.
[Hua01] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-
K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor and C. Hu, ’’Sub-50nm P-channel
FinFET’’, IEEE Transactions on Electron Devices, vol. 48 (5), pp. 880-886, 2001.
[Iij91] S. Iijima, ’’Helical microtubules of graphitic carbon’’, Nature, vol. 354, pp. 56-58, 1991.
[Ing92] G. L. Ingold and Y. V. Nazarov, chapter in ’’Single charge tunneling - Coulomb Blockade
phenomena in nanostructures’’, Plenum Press and NATO Scientific Affairs Division, pp. 21-107,
New-York NY, 1992.
[Int07a] Online: http://www.intel.com/museum/archives/history_docs/mooreslaw.htm (2007).
[Int07b] Online: http://www.intel.com/pressroom/archive/releases/20070128comp.htm (2007).

Bibliography 53
[Ion04] A. M. Ionescu, S. Mahapatra and V. Pott, ’’Hybrid SETMOS architecture with Coulomb blockade
oscillations and high current drive’’, Electron Device Letters, vol. 25 (6), pp. 411-413, 2004.
[Ion05] A. M. Ionescu and K. Banerjee (Editors), ’’Emerging Nanoelectronics: Life with and after CMOS’’,
Kluwer Academic Publishers, Springer, 2005.
[Iri04] H. Irie, K. Kita, K. Kyuno and A. Toriwni, ’’In-plane mobility anisotropy and universality under uniaxial
strains in nand p-MOS inversion layers on (100), [110], and (111) Si’’, Technical Digest of
IEDM, pp. 225-228, Washington DC, 2005.
[Jos01] E. Josse, T. Skotnicki, M. Jurczak, M. Paoli, B. Tormen, D. Dutartre, P. Ribot, A.Villaret and E.
Sondergard, ’’High performance 40 nm vertical MOSFET within a conventional CMOS process
flow’’, Proceedings of VLSI Symposium on Technology, pp. 55-56, Kyoto JP, 2001.
[Jur00] M. Jurczak, T. Skotnicki, M. Paoli, B. Tormen, J. Martins, J.-L. Regolini, D. Dutartre, P. Ribot, D.
Lenoble, R. Pantel and S. Monfray, ’’Silicon-on-Nothing (SON) - an innovative process for
advanced CMOS’’, IEEE Transactions on Electron Devices, vol. 47 (11), pp. 2179-2187, 2000.
[Kan05] A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, I. Mizushima, K. Okano, H.
Kawasaki, S. Inaba, T. Izumida, T. Kanemura, N. Aoki, K. Ishimaru, H. Ishiuchi, K. Suguro, K.
Eguchi, Y. Tsunashima, ’’Sidewall transfer process and selective gate sidewall spacer formation
technology for sub-15nm finfet with elevated source/drain extension’’, Technical Digest of IEDM,
pp. 844-847, Washington DC, 2005.
[Kav06] J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W.
Rachmady, M. Radosavljevic, U. Shah, N. Zelick and R. Chau, ’’Tri-Gate transistor architecture
with high-k gate dielectrics, metal gates and strain engineering’’, Proceedings of VLSI Symposium
on Technology, pp. 50-51, Honolulu HI, 2006.
[Kaw02] K. Kawamura, T. Kidera, A. Nakajima and S. Yokoyama, ’’Coulomb blockade effects and
conduction mechanism in extremely thin polycrystalline-silicon wires’’, Journal of Applied Physics,
vol. 91 (8), pp. 5213-5220, 2002.
[Kim01] D. H. Kim, S-K. Sung, K. R. Kim, B. H. Choi, S. W. Hwang, D. Ahn, J. D. Lee, B-G. Park, ’’Si
single-electron transistors with sidewall depletion gates and their application to dynamic singleelectron
transistor logic’’, Technical Digest of IEDM, pp. 7.3.1-7.3.4, Washington DC, 2001.
[Kir94] M. Kirihara, N. Kuwamura, K. Taniguchi and C. Hamaguchi, ’’Monte Carlo study of single electron
devices’’, International Conference of Solid State Devices and Materials, pp. 328-330, Kanagawa
JP, 1994.
[Kno91] C. M. Knoedler, ’’Helium-ion damage and nanowire fabrication in GaAs/AlGaAs heterostructures’’,
Journal of Applied Physics, vol. 68, pp. 1129-1137, 1991.
[Kog96] S. Kogan, ’’Electronic noise and fluctuations in solids’’, Cambridge University Press, Cambridge
UK, 1996.
[Kre02] F. Kreupl, A. P. Graham, G. S. Duesberg, W. Steinhögl, M. Liebau, E. Unger and W. Hönlein,
’’Carbon nanotubes in interconnect applications’’, Microelectronic Engineering, vol. 64 (1), pp. 399-
408, 2002.
[Kul75] I. O. Kulik and R. I. Shekhter, ’’Kinetic phenomena and charge discreteness effects in granular
media’’, Soviet Physics - JETP, vol. 41, pp. 308-316, 1975.
[Kuo98] J. B. Kuo and K.-W. Su, ’’CMOS VLSI Engineering Silicon-on-Insulator (SOI)’’, Kluwer Academic
Publishers, Boston MA, 1998.
[Lee04a] S-Y. Lee, S-M. Kim, E-J. Yoon, C. W. Oh, I. Chung, D. Park and K. Kim, ’’Three-dimensional
MBCFET as an ultimate transistor’’, IEEE Electron Device Letters, vol. 25 (4), pp. 217-219, 2004.
[Lee04b] S. W. Lee, D. S. Lee, R. E. Morjan, S. H. Jhang, M. Sveningsson, O. A. Nerushev, Y. W. Park and E.
E. B. Campbell, ’’A three-terminal carbon nanorelay’’, Nano Letters, vol. 4 (10), pp. 2027-2030,
2004.
[Lee05] W-H. Lee, A.Waite, H. Nii, H. M. Nayfeh, V. McGahay, H. Nakayama, D. Fried, H. Chen, L. Black,
R. Bolam, J. Cheng, D. Chidambarrao, C. Christiansen, M. Cullinan-Scholl, D. R. Davies, A.
Domenicucci, P. Fisher, J. Fitzsimmons, J. Gill, M. Gribelyuk, D. Harmon, J. Holt, K. Ida, M. Kiene,
J. Kluth, C. Labelle, A. Madan, K. Malone, P. V. McLaughlin, M. Minami, D. Mocuta, R. Murphy,
C. Muzzy, M. Newport, S. Panda, I. Peidous, A. Sakamoto, T. Sato, G. Sudo, H. VanMeer, T.
Yamashita, H. Zhu, P. Agnello, G. Bronner G. Freeman, S-F Huang, T. Ivers, S. Luning, K.
Miyamoto, H. Nye, J. Pellerin, K. Rim, D. Schepis, T. Spooner, X. Chen and M. Khare, ’’High
Performance 65 nm SOI technology with enhanced transistor strain and advanced-low-k BEOL’’,
Technical Digest of IEDM, Washington DC, 2005.

54 CHAPTER 1: Introduction
[Lee06] W. Lee, P. Su, H-Y. Chen, C.-Y. Chang, K-W. Su, S. Liu and F-L. Yan, ’’An assessment of Single-
Electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature’’,
IEEE Electron Device Letters, vol. 27 (3), pp. 182-184, 2006.
[Leo97] E. Leobandung, J. Gu, L. Guo and S. Y. Chou, ’’Wire-channel and wrap-around-gate metal-oxidesemiconductor
field-effect transistors with a significant reduction of short channel effects’’, Journal
of Vacuum Science and Technology: B, vol. 15 (6), pp. 2791-2794, 1997.
[Lik87] K. K. Likharev and V. K. Semenov, ’’Possible logic circuits based on the correlated single electron
tunneling in ultrasmall junctions’’, Extended Abstract of ISEC, pp. 128-131, Tokyo JP, 1987.
[Lik99] K. K. Likharev, ’’Single electron devices and their applications’’, Proceedings of the IEEE, vol. 87
(4), pp. 606-632, 1999.
[Llo00] S. Lloyd, ’’Ultimate physical limits to computation’’, Nature, vol. 406, pp. 1047-1054, 2000.
[Lo99] S-H. Lo, D. A. Buchanan and Y. Taur, ’’Modeling and characterization of quantization, polysilicon
depletion, and direct tunneling effects in MOSFETs with ultrathin oxides’’, IBM Journal of Research
and Development, vol. 43 (3),1999.
[Lom88] C. Lombardi, S. Manzini, A. Saporito and M. Vanzi, ’’A physically based mobility model for
numerical simulation of non planar devices’’, IEEE Transactions on CAD, vol. 7 (11), pp. 1164-
1171, 1988.
[Lun02] M. Lundstrom and Z. Ren, ’’Essential physics of carrier transport in nanoscale MOSFETs’’, IEEE
Transactions on Electron Devices, vol. 49 (1), pp. 133-141, 2002.
[Mad02] M. Madou, ’’Fundamentals of Microfabrication’’, CRC editor, 2002.
[Mah06] S. Mahapatra and A. M. Ionescu, ’’Hybrid CMOS single electron transistor device and circuit
design’’, Artech House Publishers, Boston MA, 2006.
[Mas83] G. Masetti, M. Severi and S. Solmi, ’’Modeling of carrier mobility against carrier concentration in
Arsenic-, Phosphorus- and Boron-doped Silicon’’, IEEE Transactions on Electron Devices, vol. 30,
pp. 764-769, 1983.
[Mas02a] W. P. Maszara, Z. Krivokapic, P. King, J.-S. Goo and M.-R. Lin, ’’Transistors with dual work
function metal gates by single full silicidation (FUSI) of polysilicon gates’’, Technical Digest of
IEDM, pp. 367-370, San Francisco CA, 2002.
[Mas02b] M. Masahara, T. Matsukawa, K. Ishii, L. Yongxun, H. Tanoue, K. Sakamoto, T. Sekigawa, H.
Yamauchi, S. Kanemaru and E. Suzuki, ’’15-nm-thick Si channel wall vertical double-gate
MOSFET’’, Technical Digest of IEDM, pp. 949-951, San Francisco CA, 2002.
[Mas07] MASTAR application: http://www.itrs.net/models.html (2007).
[Mel03] N. A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P. M. Petroff and J. R. Heath,
’’Ultrahigh-density nanowire lattices and circuits’’, Science, vol. 300, pp. 112-115, 2003.
[Mil11] R. Millikan, ’’On the elementary electrical charge and the Avogadro constant’’, Selected papers of
Great American Physicists, online: http://www.aip.org/history/gap/index.html, 2007.
[Miz94] T. Mizuno, J-I. Okamura, and A. Toriumi, ’’Experimental study of threshold voltage fluctuation due
to statistical variation of channel dopant number in MOSFET's’’, IEEE Transactions on Electron
Devices, vol. 41 (11), pp. 2216-2221, 1994.
[Mon01] S. Monfray, T. Skotnicki, Y. Morand, S. Descombes, M. Paoli, P. Ribot, A. Talbot, D. Dutartre, F.
Leverd, Y. Lefriec, R. Pantel, M. Haond, D. Renaud, M.-E. Nier, C. Vizioz and D. Louis, ’’First 80
nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical
performance’’, Technical Digest of IEDM, pp. 29.7.1 - 29.7.4, Washington DC, 2001.
[Mon03] S. Monfray, A. Souifi, F. Boeuf, C. Ortolland, A. Poncet, L. Militaru, D. Chanemougame and T.
Skotnicki, ’’Coulomb-Blockade in nanometric Si-film Silicon-On-Nothing (SON) MOSFETs’’,
IEEE Transactions on Nanotechnology, vol. 2 (4), 2003.
[Moo65] G. E. Moore, ’’Cramming more components onto integrated circuits’’, Electronics, vol. 38 (8), 1965.
[Moo75] G. E. Moore, ’’Progress in digital integrated electronics’’, Technical Digest of IEDM, pp. 11-13,
Washington DC, 1975.
[Moo95] G. E. Moore, ’’Lithography and the future of Moore’s law’’, Proceedings of SPIE, vol. 2437, San
Jose CA, 1995.
[Moo03] G. E. Moore, ’’No exponential is forever, but forever can be delayed’’, Digest of Technical Papers of
ISSCC, vol. 1, pp. 20-23, 2003.

Bibliography 55
[Mos07] K. E. Moselund, V. Pott, D. Bouvet and A. M. Ionescu, ’’Abrupt current switching due to impact
ionization effects in Ω-MOSFET on low doped bulk silicon’’, Proceedings of ESSDERC, pp. 287-
290, Munich DE, 2007.
[Mul86] R. S. Muller and T. I. Kamins, ’’Device Electronics for Integrated Circuits’’, John Wiley and Sons,
1986.
[Nai05] C. McNairy and R. Bhatia, ’’MonteCito: A Dual-Core, Dual-Thread Itanium Processor’’, IEEE
Micro, vol. 25 (2), pp. 10-20, 2005.
[Nam97] H. Namatsu, K. Kurihara, M. Nagase and T. Makino, ’’Fabrication of 2-nm-wide silicon quantum
wires through a combination of a partially-shifted resist pattern and orientation-dependent etching’’,
Applied Physics Letters, vol. 70 (5), pp. 619-621, 1997.
[Nee94] R. J. Needs, A. J. Read, K. J. Nash, S. Bhattarcharjee, A. Qteish, L. T. Canham and P. D. J. Calcott,
’’A first-principles study of the electronic properties of silicon quantum wires’’, Physica A:
Statistical and Theoretical Physics, vol. 207 (1-3), pp. 411-414, 1994.
[Neh05] K. Nehari, N. Cavassilas, J. L. Autran, M. Bescond, D. Munteanu and M. Lannoo, ’’Influence of
band-structure on electron ballistic transport in silicon nanowire MOSFET's: an atomistic study’’,
Proceedings of ESSDERC, pp. 229-232, Grenoble FR, 2005.
[Nej03] H. Nejo, P. Dorozhkin and H. Hori, ’’Observation of Coulomb Blockade and interference using a
carbon nanotube tip’’, Japanese Journal of Applied Physics, vol. 42, pp. 4743-4747, 2003.
[Nik05] D. E. Nikonov and G. I. Bourianoff, ’’Spin gain transistor in ferromagnetic semiconductors - the
semiconductor Bloch-equations approach’’, IEEE Transactions on Nanotechnology, vol. 4 (2), pp.
206-214, 2005.
[Oka05] K. Okano, T. Izumida, H. Kawasaki, A. Kaneko, A. Yagishita, T. Kanemura, M. Kondo, S. Ito, N.
Aoki, K. Miyano, T. Ono, K. Yahashi, K. Iwade, T. Kubota, T. Matsushita, I. Mizushima, S. Inaba,
K. Ishimaru, K. Suguro, K. Eguchi, Y. Tsunashima and H. Ishiuchi, ’’Process integration technology
and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and
20 nm gate length’’, Technical Digest of IEDM, pp. 721-724, Washington DC, 2005.
[Osb98] C. M. Osburn and K. R. Bellur, ’’Low parasitic resistance contacts for scaled ULSI devices’’, Thin
Solid Films, vol. 332, pp. 428-436, 1998.
[Pan04] P. Pandey, B. B. Pal and S. Jit, ’’A new 2-D model for the potential distribution and threshold
voltage of fully depleted short-channel Si-SOI MESFETs’’, IEEE Transactions on Electron Devices,
vol. 51 (2), pp. 246-254, 2004.
[Par01a] J.-T. Park, C. A. Colinge and J.-P. Colinge, ’’Comparison of gate structures for short-channel SOI
MOSFETs’’, IEEE International SOI Conference, pp. 115-116, Durango CO, 2001.
[Par01b] J.-T. Park, J.-P. Colinge and C. H. Diaz, ’’Pi-Gate SOI MOSFET’’, IEEE Electron Device Letters,
vol. 22 (8), pp. 405-406, 2001.
[Par02] J. Park, A. N. Pasupathy, J. I. Goldsmith, C. Chang, Y. Yaish, J. R. Petta, M. Rinkoski, J. P. Sethna,
H. D. Abruña, P. L. McEuen and D. C. Ralph, ’’Coulomb blockade and the Kondo effect in singleatom
transistors’’, Nature, vol. 417, pp. 722-725, 2002.
[Par03] M. C. B. Parish and M. Forshaw, ’’Physical constraints on magnetic quantum cellular automata’’,
Applied Physics Letters, vol. 83 (10), pp. 2046-2048, 2003.
[Par06] D. Park, ’’3 dimensional GAA transitors: twin silicon nanowire MOSFET and multi-bridge-channel
MOSFET’’, IEEE International SOI Conference, pp. 131-134, Niagara Falls NY, 2006.
[Pid06] The International Roadmap for Semiconductor, ’’Process Integration, Devices and structures’’, 2006
Edition, available at http://www.itrs.net/, 2006.
[Plu01] J. D. Plummer and P. B. Griffin, ’’Material and process limits in silicon VLSI technology’’,
Proceedings of the IEEE, vol. 89 (3), pp. 240-258, 2001.
[Por00] D. Porath, A. Bezryadin, S. de Vries and C. Dekker, ’’Direct measurement of electrical transport
through DNA molecules’’, Nature, vol. 403, pp. 635-638, 2000.
[Pot91] H. Pothier, P. Lafarge, P. F. Orfila, C. Urbina, D. Esteve and M. H. Devoret, ’’Single electron pump
fabrication with ultrasmall normal tunnel junctions’’, Physica B, vol. 169, pp. 573-574, 1991.
[Qia00] L. Qiang, Y. C. Yeo, P. Ranade, H. Takeuchi, T.-J. King, C. Hu, S. C. Song, H. F. Luan and D.-L.
Kwong, ’’Dual-metal gate technology for deep-submicron CMOS transistors’’, Proceedings of VLSI
Symposium on Technology, pp. 72-73, Honolulu HI, 2000.
[Rei02] J. Reichert, R. Ochs, D. Beckmann, H. B. Weber, M. Mayor and H. v. Löhneysen, ’’Driving current
through single organic molecules’’, Physical Review Letters, vol. 88 (17), 2002.

56 CHAPTER 1: Introduction
[Roy94] S. A. Roy, ’’Simulation tools for the analysis of single electron systems’’, University of Glasgow
UK, PhD dissertation thesis, 1994.
[Rim00] K. Rim, J. L. Hoyt and J. F. Gibbons, ’’Fabrication and analysis of deep submicron strained-Si N-
MOSFET’s’’, IEEE Transactions on Electron Devices, vol. 47 (7), pp. 1406-1415, 2000.
[Sai02] M. Saitoh, T. Murakami and T. Hiramoto, ’’Effects of oxidation process on the tunneling barrier
structures in room-temperature operating silicon single-electron transistors’’, IEEE Transactions on
Nanotechnolgy, vol. 1 (4), pp. 214-218, 2002.
[Sch01] T. Schulz, W. Rösner, L. Risch, A. Korbel and U. Langmann, ’’Short-Channel vertical sidewall
MOSFETs’’, IEEE Transactions on Electron Devices, vol. 48 (8), pp. 1783-1788, 2001.
[Sch04] A. Schmid and Y. Leblebici, ’’Robust circuit and system design methodologies for nanometer-scale
devices and single-electron transistors’’, IEEE Transactions on Very Large Scale Integration
Systems, vol. 12 (11), 2004.
[She93] M.-Y. Shen and S.-L. Zhang, ’’Band gap of a silicon quantum wire’’, Physics Letters A, vol. 176 (3-
4), pp. 254-258, 1993.
[Shi00] K. Shiraishi, M. Nagase, S. Horiguchi, H. Kageshima, M. Uematsu, Y. Takahashi and K. Murase,
’’Designing of silicon effective quantum dots by using the oxidation-induced strain: a theoretical
approach’’, Physica E, vol. 7 (3), pp. 337-341, 2000.
[Sin06] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, C. H. Tung, K. M. Hoe, S.
R. Omampuliyur, D. Tripathi, A. O. Adeyeye, G. Q. Lo, N. Balasubramanian and D. L. Kwong,
’’Ultra-narrow silicon nanowire gate-all-around CMOS devices: impact of diameter, channelorientation
and low temperature on device performance’’, Technical Digest of IEDM, pp. 1-4, San
Francisco CA, 2006.
[Sko93] T. Skotnicki, G. Merckel and C. Denat, ’’MASTAR - A model for analog simulation of subthreshold,
saturation and weak avalanche regions in MOSFETs’’, VPAD International Workshop, pp. 146-147,
Nara JP, 1993.
[Sko00] T. Skotnicki, ’’Heading for decananometer CMOS - Is navigation among icebergs still a viable
strategy?’’, Proceedings of ESSDERC, pp. 19-33, Cork IE, 2000.
[Sko05] T. Skotnicki, ’’CMOS technologies for end of roadmap’’, EPFL Lecture, 2005.
[Son06] J. Y. Song, W. Y. Choi, J. H. Park, J. D. Lee and B.-G. Park, ’’Design optimization of gate-all-around
(GAA) MOSFETs’’, IEEE Transactions on Nanotechnology, vol. 5 (3), pp. 186-191, 2006.
[Sug04] S. Sugahara and M. Tanaka, ’’A spin metal-oxide-semiconductor field-effect transistor using halfmetallic-ferromagnet
contacts for the source and drain’’, Applied Physics Letters, vol. 84 (13), pp.
2307-2309, 2004.
[Suk05] S. D. Suk, S.-Y. Lee, S.-M. Kim, E.-J. Yoon, M.-S. Kim, M. Li, C. W. Oh, K. H. Yeo, S. H. Kim, D.-
S. Shin, K.-H. Lee, H. S. Park, J. N. Han, C. J. Park, J.-B. Park, D.-W. Kim, D. Park and B.-I. Ryu,
’’High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk
Si wafer, characteristics, and reliability’’, Technical Digest of IEDM, pp. 717-720, Washington DC,
2005.
[Sze02] S. M. Sze, ’’Semiconductor devices: Physics and Technology’’, John Wiley & Sons, 2 nd Edition,
2002.
[Tak96] Y. Takahashi, H. Namatsu, K. Kurihara, K. Iwadate, M. Nagase and K. Murase, ’’Size dependence
of the characteristics of Si Single-Electron Transistors on SIMOX substrates’’, IEEE Transactions
on Electron Devices, vol. 43 (8), pp. 1213-1217, 1996.
[Tak01] K. Takayanagi, Y. Kondo and H. Ohnishi, ’’Suspended gold nanowires: ballistic transport of
electrons’’, JSAP International, vol. 3, pp. 3-8, 2001.
[Tan00] X. Tang, X. Baie, J.-P. Colinge, F. Van de Wiele and V. Bayot, ’’Quantum effects in SOI single-hole
transistors’’, Proceedings of ESSDERC, pp. 220-223, Cork IE, 2000.
[Tan03] T. Tanaka, Y. Ohno, S. Kishimoto, K. Maezawa and T. Mizutani, ’’Experimental demonstration of
capacitor-coupled resonant tunneling logic gates for ultra-short gate-delay operation’’, Japanese
Journal of Applied Physics, vol. 42 (11), pp. 6766-6771, 2003.
[Tau97] Y. Taur and E. J. Nowak, ’’CMOS devices below 0.1 µm: how high will performance go?’’,
Technical Digest of IEDM, pp. 215-218, Washington DC, 1997.
[Tau98] Y. Taur and T. H. Ning, ’’Fundamentals of Modern VLSI Devices’’, Cambridge University Press,
Cambridge UK, 1998.
[Tiw95] S. Tiwari, F. Rana, C. Wei, K. Chan and H. Hanafi, ’’A low power 77K nano-memory with single
electron nano-crystal storage’’, Proceedings of ESSDERC, pp. 50-51, The Hague NL, 1995.

Bibliography 57
[Top06] News, ’’Top five in physics’’, Nature, vol. 441, pp. 265, 2006.
[Uch01] K. Uchida, J. Koga, R. Ohba, S. Takagi and A. Toriumi, ’’Silicon single-electron tunneling device
fabricated in an undulated ultrathin silicon-on-insulator film’’, Journal of Applied Physics, vol. 90
(7), pp. 3551-3557, 2001.
[Uch02] K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata and S. Takagi, ’’Experimental study on
carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5
nm’’, Technical Digest of IEDM, pp. 47-50, San Francisco CA, 2002.
[Wak03] H. Wakabayashi, S. Yamagami, N. Ikezawa, A. Ogura, M. Narihiro, K. Arai, Y. Ochiai, K. Takeuchi,
T. Yamamoto and T. Mogami, ’’Sub-10-nm planar-bulk-CMOS devices using lateral junction
control’’, Technical Digest of IEDM, pp. 20.7.1 - 20.7.3, Washington DC, 2003.
[Was97] C. Wasshuber, H. Kosina and S. Selberherr, ’’SIMON: a simulator for single-electron tunnel devices
and circuits’’, IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems,
vol. 16, pp. 937-944, 1997.
[Was01] C. Wasshuber, ’’Computational Single-Electronics’’, Springer Verlag, Wien AT, 2001.
[Was05] R. Waser (Editor), ’’Nanoelectronics and information technology’’, Wiley-VCH Verlag, Weinheim
DE, 2005.
[Wat03] H. Watanabe, K. Matsuzawa and S. Takagi, ’’Scaling effects on gate leakage current’’, IEEE
Transactions on Electron Devices, vol. 50 (8), pp. 1779-1784, 2003.
[Web06] W. M. Weber, L. Geelhaar, A. P. Graham, E. Unger, G. S. Duesberg, M. Liebau, W. Pamler, C.
Chèze, H. Riechert, P. Lugli and F. Kreupl, ’’Silicon-nanowire transistors with intruded nickelsilicide
contacts’’, Nano Letters, vol. 6 (12), pp. 2660-2666, 2006.
[Wid04] J. Widiez. F. Daugé. M. Vinet. T. Poiroux. B. Previtalil, M. Mouis and S. Deleonibus, ’’Experimental
gate misalignment analysis on double gate SOI MOSFETs’’, IEEE International SOI Conference,
pp. 185-186, Charleston SC, 2004.
[Wil00] G. D. Wilk, R. M. Wallace and J. M. Anthony, ’’Hafnium and zirconium silicates for advanced gate
dielectrics’’, Journal of Applied Phyics, vol. 87 (1), pp. 484-492, 2000.
[Wil01] G. D. Wilk, R. M. Wallace and J. M. Anthony, ’’High-k gate dielectrics: Current status and materials
properties considerations’’, Journal of Applied Physics, vol. 89 (10), pp. 5243-5275, 2001.
[Won97] H.-S. P. Wong, K. K. Chan, and Y. Taur, ’’Self-aligned (top and bottom) double-gate MOSFET with
a 25 nm thick silicon channel’’, Technical Digest of IEDM, pp. 427-430, Washington DC, 1997.
[Xia06] J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan and C. M. Lieber, ’’Ge/Si nanowire heterostructures as highperformance
field-effect transistors’’, Nature, vol. 441, pp. 489-493, 2006.
[Yan93] K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai and K. Seki, ’’A room-temperature Single-
Electron Memory device using fine-grain polycrystalline silicon’’, Technical Digest of IEDM, pp.
541-544, Washington DC, 1993.
[Yan97] I. Y. Yang, C. Vieri, A. Chandrakasan and D. A. Antoniadis, ’’Back-Gated CMOS on SOIAS for
dynamic threshold voltage control’’, IEEE Transactions on Electron Devices, vol. 44 (5), pp. 822-
831, 1997.
[Yan98] K. Yano, T. Ishii, T. Sano, T. Mine, F. Murai, T. Kure and K. Seki, ’’A 128Mb early prototype for
gigascale single-electron memories’’, Digest of Technical Papers of ISSCC, pp. 344-346, 1998.
[Yan02] F.-L. Yang, H.-Y. Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang, H.-K. Chiu, C.-C. Lee, C.-C. Chen,
H.-T. Huang, C.-J. Chen, H.-J. Tao, Y.-C. Yeo, M.-S. Liang and C. Hu, ’’25 nm CMOS Omega
FETs’’, Technical Digest of IEDM, pp. 255-258, San Francisco CA, 2002.
[Yan04] F.-L. Yang, D.-H. Lee, H.-Y. Chen, C.-Y. Chang, S.-D. Liu, C.-C. Huang, T.-X. Chung, H.-W. Chen,
C.-C. Huang, Y.-H. Liu, C.-C. Wu, C.-C. Chen, S.-C. Chen, Y.-T. Chen, Y.-H. Chen, C.-J. Chen, B.-
W. Chan, P.-F. Hsu, J.-H. Shieh, H.-J. Tao, Y.-C. Yeo, Y. Li, J.-W. Lee, P. Chen, M.-S. Liang and C.
Hu, ’’5nm-gate nanowire FinFET’’, Proceedings of VLSI Symposium on Technology, pp. 196-197,
Honolulu HI, 2004.
[Yu06] Y. S. Yu, H. W. Kye, B. N. Song , S-J. Kim and J-B. Choi, ’’A new multi-valued static random
access memory (MVSRAM) with hybrid circuit consisting of single-electron (SE) and MOSFET’’,
Proceedings of ISCAS, pp. 4575-4578, Kos GR, 2006.
[Zha03] S. Zhang, X. Lin, R. Huang, R. Han and M. Chan, ’’A self-aligned, electrically separable doublegate
MOS transistor technology for dynamic threshold voltage application’’, IEEE Transactions on
Electron Devices, vol. 50 (11), pp. 2297-2300, 2003.
[Zhi05] V. Zhirnov, J. A. Hutchby, G. I. Bourianoff and J. E. Brewer, ’’Emerging research logic devices’’,
IEEE Circuits & Devices Magazine, vol. 21 (3), pp. 37-46, 2005.

Chapter 2
Silicon nanowire for MOS/SET
combined functionality
In this second chapter, we study the silicon-based single electron transistor. The first part is a
detailed review of main technology and modelling approaches used for the integration of SET. It
seems highly relevant to present how engineers try to control Coulomb blockade in nano-metric
silicon structures. Typical SET fabrication technologies include pattern dependent oxidation, nanolithography,
top-down silicon nanowires and silicon wire growth. This chapter shows also how
strong is the link between physics, modelling and technology, and why these should never be
disconnected. The diversity in SET technology and SET modelling impose a very careful study of
previous reports.
Then, crucial points of the EPFL silicon nanowire are presented. We show how we use finite element
analysis for SET/MOS device simulation. Full 3D simulation tools of integration process are still not
available, but some key computing points, like corners effect in silicon triangular cross-sections or
inversion levels in nano-scale silicon channels are efficiently addressed with TCAD tools.
Finally, a short description of a unique hybrid micro-electro-mechanical SET device - the SET-
NEMS architecture - is proposed and discussed.

60 CHAPTER 2: Silicon nanowire for MOS/SET combined functionality
2.1 Bridge the gap with the single electron transistor
This chapter focuses on the geometry and modelling of silicon nanowire transistors. We propose first
a summary of mono-crystalline silicon-based SET, including a state-of-the-art review of the
proposed architectures, integration processes and device performances.
Our devices modelling is based on both analytical and numerical analysis. Main results of hybrid
MOS/SET model concepts have been published at ESSDERC 2006 [Pot06].
Finally, we shortly present in this chapter the architecture of a SET-NEMS device that was originally
proposed at IEDM 2003 [Mah03].
Silicon is currently the main material used for the integration of single electron devices. The well
established CMOS fabrication technology is ideal for making nano-scale structures. However, both a
reproducible SET technology and a 3D full-device silicon SET model are still completely lacking.
The SET is not a mature device and no technology has proved good enough results for industrial
applications. The origin of these difficulties comes from the extremely small size of the SET and
from multi-physical effects that interfer in the charge transport (interface scattering, single doping
effect, Coulomb blockade, quantization). The two boxes presented in Figure 2.1 show a melting-pot
of major modelling and technology approaches proposed in the literature. We will discuss these
approaches and then we motivate our original ideas.
Poisson
equation
Random
dopant
fluctuation
Silicon nanowire
SET modelling
Non-equilibrium
Green's function
formalism
Figure 2.1: Main silicon nanowire SET modelling and technology proposed during the last 15 years.
How to gap modelling and technology?
To conclude this introduction, we would like to emphasize the link between an hourglass and the
single electron transistor. This is an extremely elegant image of an SET.
Victorian Hour Glass
XIX th Century
Schrödinger equation
1D-2D-3D quantization
Gravity
Orthodox
theory
Multi-configurational
self consistent
Green's function
Source
Figure 2.2: Is the single electron transistor the
hourglass of the XXI st Century?
e -
e -
e -
e -
e -
e -
e -
Drain
Atomistic
modelling
Electric
field
Single Electron Transistor
XXI st Century
Bridge the
gap
Top-down
nanowires
Vertical
SET
STM/AFM
nano-oxidation
Pattern dependent
oxidation
Silicon-based
SET technology
Silicon nanowires
growth
E-beam
lithography
Autoaligned
techniques
Electrically
induced SET
Quantum modelling of SET can be compared to
a sand hourglass, as shown in Figure 2.2. First
hourglasses have been built during the XIth Century to measure time at sea. About thousand
years later, the same geometry was used in
single electronics: a junction between two large
carrier reservoirs. At the junction, quantization
of the carriers (sand grains or electrons) is taken
into account. The scale difference between the
two devices is about 108 !
If modelling of a realistic single electron
transistor is considered as a challenging task,
then the detailed mechanics of the sandglass is
also a very famous physics problem [Mil96].

The crystalline silicon SET: geometry and architecture 61
2.2 The crystalline silicon SET: geometry and architecture
This section presents main geometries and fabrication process proposed for the integration of silicon
single electron devices. The gate-all-around original technology we developed is in the dedicated
chapter: Hybrid SET/MOS technology.
Silicon is currently the main SET platform. The plot presented in Figure 2.3 is a statistical evolution
of the number of publications having the key word Single Electron in their titles. This statistic is an
easy way to highlight the true impact of an emerging technology, as Single Electronics. The research
is made for the last 20 years in three representative scientific publishers: IEEE Explorer 1 , Science-
Direct 2 and SCIENCE 3 . The trend is a slight increase of published references.
Number of references
50
40
30
20
10
0
Key word = Single electron
IEEE
Science Direct
SCIENCE
Figure 2.3: Representative evolution of single electronics publications plotted for the last 20 years.
2.2.1 Pattern dependent oxidation of SOI nano-structures
The pattern dependent oxidation (PADOX) technology is with no doubt the most advanced
technology developed for the fabrication of the silicon SET. This was initially studied by Japanese
research groups, essentially by the NTT company. PADOX consists in oxidizing a SOI nanostructure
into a double constricted shape. Many remarkable reports have been published for more
than 12 years, emphasizing main variants of the PADOX. In 1996, the paper [Tak96] is
demonstrating how pattern dependent oxidation of SOI nanowires is efficiently used for the
fabrication of SET. In Figure 2.4, we show the original NTT SET design (the gate is a deposited
LPCVD polysilicon layer and is not displayed) and associated g m -V G characteristics.
Figure 2.4: (Left) 3D view of a PADOX SET transistor, by [Tak96]. (Right) Measured g m-V G
characteristics at various temperatures. The original device wire length is 50nm.
1. See: http://ieeexplore.ieee.org/Xplore/dynhome.jsp
2. See: http://www.sciencedirect.com/
3. See: http://www.sciencemag.org/
1988 1992 1996 2000 2004
Year of publications

62 CHAPTER 2: Silicon nanowire for MOS/SET combined functionality
Silicon-on-insulator SET defined by the PADOX process are always structured in the same fashion:
1. Definition of a SOI nanowire (Figures 2.4 and 2.6) or a SOI point contact pattern (Figure
2.5). SOI wires are usually patterned with high resolution e-beam lithography.
2. Dry atmosphere oxidation. This creates the two SET junctions. A single or multiple
silicon dots in the center of the channel act as silicon SET islands.
Silicon oxidation is a stress dependent phenomena. Stress analysis during oxidation is
used to shape the silicon in an ideal junction-island-junction SET geometry. The PADOX
oxide usually serves also as a gate oxide.
A large aspect ratio silicon wire (wire width >> silicon thickness) results in twin parallel
silicon wires after oxidation. This effect is called the vertical PADOX (V-PADOX).
3. Deposition and patterning of a single top gate (Figure 2.6) or multiple lateral gates.
Another PADOX device is presented in Figure 2.6. In this work, reported in [Ish97], authors are
initially patterning - by e-beam and anisotropic etching - a single contact channel between two SOI
larger pads. According to the authors, such a geometry results in a single dot SET after oxidation.
Quantum dot and SET capacitances are extracted from electrical measurements. Process device
improvement, with a less than 4.4nm single island diameter and a large 259meV charging energy, is
reported in 2001 in [Sai01].
Figure 2.5: (Left) Point contact SOI SET transistor proposed by [Ish97]. (Right) I D vs. V G -V DS plot
measured at T=4.2K. Clear I D -V G rhombus shapes and I D -V DS current plateaux are observed.
Further development in the PADOX process consists in accurately control the SET island dimension
to have reproducible and foreseeable characteristics. The increase of the operational temperature is
also a great challenge.
As an example, the report [Nam03] highlights the role of the nanowire dimension in transport
characteristics. Process pictures in Figure 2.6 are ultra-precisely defined silicon nanowires. After
PADOX and a gate stack integration, a measurement statistic is realized. Large wires are not
sensitive to Coulomb blockade, mid-range wires are ideal oscillating SET, while over-oxidized wires
are non-conductive at all. This paper shows how the range of SET island dimension is limited to a
very tiny window.
Figure 2.6: (Left) SOI nanowires defined by high resolution e-beam lithography [Nam03] on
negative HSQ resist. (Right) A tilted SEM view of a nanowire SET transistor.

The crystalline silicon SET: geometry and architecture 63
Reports on PADOX-processed SET are not only focused on the technology, but also on other aspects,
like quantum mechanics, process and device simulation or basic SET/CMOS circuitry.
The two papers [Shi00] and [Hor01] propose hypothesis on the formation of tunnel junctions by
silicon oxidation. In fact, it is difficultly understandable how a continuous nano-constricted silicon
wire acts as a tunnel junction at low temperature. The junctions resulting from a continuous silicon
nanowire have a completely different nature, compared with ideal dielectric tunnel junctions.
As shown in Figure 2.7, a combined effect of 1D quantization and strained silicon is necessary to
shape the silicon conduction band in a double junction structure. The central part of the wire behaves
as a quantum well for the electrons.
Bulk silicon
Unstrained
silicon wire
Strained
silicon wire
S
S
1D confined
silicon wire
D
Figure 2.7: The blockade of charges in PADOX nanowires is explained by the combined effect of (i)
1D quantization, resulting in the conduction band splitting and (ii) compressive strain in the central
part of the wire, reducing the silicon band-gap. Geometries and associated band diagrams are shown.
The complete model of the combined 1D-quantized and strained silicon is described in [Hor01].
Authors obtain a band-gap reduction of about 0.1eV (silicon band-gap=1.1eV at T=300K) for a
100nm long silicon wire, 10nm x 10nm in the cross-section, and a large 1% compressive strain. They
consider a gaussian distributed strain with a maximum strain density in the center of the wire.
One-dimensional singularities in silicon can be analytically calculated, as presented in [Was05]. The
smaller the dimensions, and the larger the band splitting. However, the distance between the different
split conduction bands is not constant. The impact of 1D band splitting is now considered in many
silicon nanowire/FinFET transistors. The paper [Col06] is very clearly showing how electrons are
sensitive to 1D density of states singularities (See Section 4.3.2).
However, due to the small energy difference between two successive bands, oscillating
characteristics corresponding to the progressive filling of sub-bands are only observed at low
temperature, where the energy of electrons kT is comparable to the sub-band energy differences. The
finite elements analysis is the best way to simulate any given wire geometry.
Other PADOX reports include various interesting discussions. The paper [Tak02] is a valuable
review of silicon single-electron devices and geometries. The reference [Mor01] highlights the
evidence of activated conduction in silicon SET. Indeed, contrary to metal-based SET, silicon-based
SET junction have temperature dependent characteristics. The [Mor01] paper also show that PADOX
SET may have multiple induced islands. A complete analysis of temperature vs. current is shown and
different activation mechanisms are discussed.
Finally, SET/CMOS circuit reports have also been recently proposed. As a good example, we can
mention [Nis04]. Authors propose and experimentally demonstrate a basic method to automatically
control the oscillation phase of SET, and so to cancel any parasitic background charge effect.
D
S
Strain: bandgap reduction
1D confined silicon
wire + strain
S
E Si
1D band splitting
D
D
E C
E V
E C
E V
E C
E V

64 CHAPTER 2: Silicon nanowire for MOS/SET combined functionality
2.2.2 Coulomb Blockade in MOS transistors
In this section, we show some examples of Coulomb blockade sensitive MOS transistors. All papers
reported in this section are demonstrating how advanced MOS devices may exhibit single electron
characteristics at low V DS bias and at cryogenic temperature, while standard n-type/p-type MOS
characteristics are observed at room temperature. The combined SET/MOS effect has to be clearly
discussed, as well as the origin of the Coulomb island and the SET junctions. In a MOS structure, the
channel of the transistor could be electrostatically turned into a quantum dot at low temperature.
One of the first detailed report on controlled single-electron effects in ultra-short silicon FET was
published in 2003 by STMicroelectronics and CEA Grenoble, in [Boe03]. Transistors are integrated
on a low-doped bulk substrate and have a 16nm long channel. At low temperature, non-overlapped
source and drain regions act as tunnel junctions. The electrostatic potential along the channel is
simulated and clearly prove the isolation of a dot by two potential barriers. I D -V G oscillations are
observed at T=4.2K and C G =23aF is extracted from the histogram of peak spacing. This capacitance
corresponds to a factor of three smaller than the nominal channel capacitance. Hundreds of
oscillations are observed for both nMOS and pMOS transistors. At low temperature, a double I DS
contribution exists in the device: a CB fluctuation contribution and a continuous variation reflecting
changes in the induced barriers height.
Non-overlapped silicon-on-nothing (SON) MOSFET have also been investigated for single-electron
applications. This device, reported in [Mon03], exhibit also a potential camel’s back shape along the
channel at cryogenic temperature and at low V DS . The small channel volume acts as an SET quantum
box. As in [Boe03], a double drive an oscillating currents are observed.
Silicon-on-insulator MOSFET with nano-constrictions have also shown Coulomb oscillations at low
temperature. As an example, devices and measurements published by CEA Grenoble in [Jeh03] show
Coulomb blockade in silicon devices even without intentional tunnel barriers. This paper is
particularly focusing on the role of access resistances in transport characteristics. In their conclusion,
authors demonstrate a Coulomb charging energy inversely proportional to the channel-gate overlap
surface. A smaller channel dimension (both W and L) will result in an increase of the Coulomb
energy, and so in a higher operational temperature SET.
In 2005, a very remarkable study of silicon nanowire transistor operating at cryogenic temperature
was proposed again by CEA Grenoble [Hof05]. This report shows how to determine the occurrence
of single traps in the silicon channel, by exploiting the SET extreme sensitivity to offset charges.
This work represents therefore a step towards the characterization of individual dopant atoms in
ultra-scaled MOSFET. A device TEM cross-section and a transconductance vs. gate voltage are
proposed in Figure 2.8. Single traps are detected by anomalous CB characteristics.
Figure 2.8: (Left) Transmission electron micrograph along a silicon nanowire transistor and
equivalent electrical model [Hof05]. (Right) Transconductance vs. gate voltage characteristics
measured at T=300K and 0.7K. Anomalous oscillations in the CB plot are highlighted by circles.
The next example of observed Coulomb blockade in MOS transistors was published in 2006 by the
two Taiwanese groups of Chiao-Tung University and TSMC [Lee06]. Coulomb blockade is observed
for the first time at room temperature in ultra-scaled FinFET (H fin=40nm, W fin=25nm and
L G=30nm). An undoped region under the spacers act as two electrostatic tunnel barriers, while the
equivalent SET island is the silicon fin. As in previous reports, the shape of this quantum box may be
deformed by the applied gate voltage, because of barriers modulation. A device plot is shown in

The crystalline silicon SET: geometry and architecture 65
Figure 2.9 (left). On the same Figure is reported a g m /V DS vs. V G curve measured at T=20°C. Again,
a combined contribution of MOS and SET is observed in the drain current characteristics. This recent
report is a highly promising work but this may also worry CMOS experts! From one side, room
temperature oscillations in ultra-scaled MOS transistors may be considered as a parasitic effect, but
on the other side this also signifies that a simple and well-designed MOS transistor may be directly
used as a single-electron transistor.
Figure 2.9: (Left) FinFET MOS transistor geometry investigated in [Lee06] and cross-section view
along the channel direction. (Right) Periodic CB oscillations measured at T=20°C. In the inset, a
power spectrum density FFT transform representing the distribution of peak spacing ΔV G .
Other groups - like EPFL - have reported Coulomb blockade in MOS transistors. The last example is
a work from LMU Munich [Til03]. Authors study electrical transport within 10nm wide and 500nm
long nanowire transistors defined on p-type SIMOX wafers. The wire is passivated by 15nm grown
oxide. Then, 40nm of oxide and a metallic front gate are deposited. A dip in the I DS -V DS curve is
observed around V DS =0 and is attributed to shallow tunneling barriers within the wire. This study
shows also, that despite an imperfect nanowire processing (contact resistances, process variability,
edge roughness), pronounced quantum effects are visible.
2.2.3 Highly doped silicon nanowires
Coulomb blockade oscillations on uniformly doped SOI nanowires have been observed and
discussed by different groups. Contrary to the MOS geometry, where pn junctions are introduced
during the process, fully doped wires are also sensitive to Coulomb blockade. Different physical
models of tunnel barriers are proposed, as silicon nano-constrictions, strain combined with 1D
quantization or the unique role of single dopant atoms at nano-scale.
Side gate 1
200nm
2DEG
0DEG
1DEG
2DEG
Side gate 2
Figure 2.10: SEM picture of a SET structure, by
[Aug00]. The central 0DEG quantum dot is
about 20nm diameter. 10nm wide 1DEG silicon
wires are designed as tunnel barriers.
In the paper [Aug00] published by the
University of Tübingen, authors investigate
highly doped silicon SET with geometrically
well defined tunnel barriers. The devices are
fabricated on SOI wafers and are 3x1018cm-3 ntype
doped. As shown in Figure 2.10, two side
gates are controlling the device electrostatic.
Source and drain are 2D Electron Gas (2DEG),
the tunnel barriers 1DEG and the central dot is
considered as a 0DEG with fully quantized
energy levels. This kind of device behaves
either as a single or as a multiple dot SET with
randomly formed barriers. This depends on the
geometrical barriers resolution. The maximum
device operational temperature is about 28K.

66 CHAPTER 2: Silicon nanowire for MOS/SET combined functionality
The real advantage to use highly doped silicon nanowire is demonstrated in 2001, in the report
[Eva01]. In this paper, the origin of barriers and islands is attributed to single dopant atoms.
Figure 2.11: Potential fluctuation along a 2DEG
10 19 cm -3 doped silicon wire, by [Eva01].
The study of randomly distributed electron islands in highly doped silicon nanowires has been
extended by other R&D groups, and more particularly in devices optimization and scaling. For
example, the paper [Til01] shows how a double gate nanowire transistor, including a top metallic
gate and a side gate, has been implemented and characterized. Almost periodic conductance
oscillations are observed in 500nm long and 25nm x 10nm in cross-section As-doped silicon
nanowires. An I D -V D Coulomb gap is also measured at low temperature (T

The crystalline silicon SET: geometry and architecture 67
Electrically induced SET proposed in [Kim01] have oscillations at temperatures higher than 77K.
SET basic logic operations are demonstrated at T=10K. Compared with other Si-SET technologies,
the reproducibility of observed characteristics is quite good. Furthermore, as the island is an induced
dot, then the lithographic resolution is not extremely critical.
This technique has been continued, as reported in 2004 in [Hu04]. In this new process, variations in
the metal gate and an improved floating gate integration are introduced. This device exhibits MOS
characteristics at room temperature and Coulomb blockade at cryogenic temperature. However, deep
analysis of measured data and the relatively large dimension (~30nm diameter) of the induced
channel show that multiple islands may be induced in the channel part of the wire.
2.2.5 Gate-all-around silicon nanowires
Oscillating characteristics have been very recently reported in gate-all-around (GAA) silicon
nanowires. The core of our original EPFL GAA technology is described in Section 3.4 and
experimental data in Chapter 4. However, the group of Singh and Kwong, from Singapore Science
Park, has measured nano-scale GAA devices with low temperature fluctuations [Sin06], as shown in
Figure 2.13. Unfortunately, authors are still not discussing the exact origins of the observed low
temperature fluctuations.
5nm
Figure 2.13: (Left) TEM micrograph of a triangular silicon nanowire surrounded by 4nm of oxide.
(Right) Temperature dependent I D -V G characteristics of a 6nm diameter silicon nanowire, measured
at V D =50mV. The gate length is 350nm. Both pictures are from [Sin06].
The gate-all-around geometry is now a very topical research subject. This structure offers an ideal
channel control, for both MOS and SET devices. The Chapter 1.4.5 is introducing GAA-MOS
transistors and demonstrates how this is a solution for advanced CMOS applications.
2.2.6 Other silicon SET integration technologies
The technologies presented in the previous sections are currently the most advanced and well-known
methods used for the integration of silicon SET. Others approaches are reported in the literature.
These contributions seem surprising, sometimes not realistic or even funny, but they have all the
merit to explore original technics and geometries. This includes:
• The vertical SET: this device was investigated in 1997 by NTT and reported in [Aus97].
The vertical SET has however attracted much less attention than the planar SET.
• Nano-fabrication with proximal probes: Atomic Force Microscopy (AFM) and Scanning
Tunneling Microscopy (STM) are quite attractive for local processing. Localized nanooxidation
for single electron applications has been reported under specific conditions, for
example in [Mat97]. Various materials and device geometries have been proposed and
show encouraging results. However, such a fabrication process cannot be exploited for
large scale integration.
• Growth of silicon nanowires: The catalytic growth of single-crystal silicon nanowires has
been proposed by different groups. A very clear and efficient process is described in
[Cui00]. This paper shows two-terminal characterization of Si nanowire transistors, where
the conduction is controlled by a metallic gate. No evidence for low temperature Coulomb
blockade is however reported. Potential applications of Si nanowire as a SET design are
discussed. One-dimensional nanowires, used as emerging devices for logic applications,
are described in Section 1.5.6.

68 CHAPTER 2: Silicon nanowire for MOS/SET combined functionality
2.3 Silicon nanowire devices comparison
The large variety of devices presented in the previous section shows how large is the diversity of
silicon technologies. This section compares performances to emphasize advantages and limitations
of each technology. This includes also EPFL devices integrated and measured during this thesis
(Measurement are in Chapter 4).
The parameters (island capacitance, tunnel barrier resistances,...) are extracted with the Orthodox
theory (see Section 1.5.2). Despite the fact that Orthodox theory does not perfectly fit for siliconbased
SET, this model has been used by authors during many years and serves as a reference. Field
effects in silicon or tunnel barrier height modulation are not taken into account by this formalism.
We would like also to suggest, as a remarkable example, the new approach proposed in [Ind07] for
the computation of Coulomb effects in silicon wires. This new model is based on multiconfigurational
self-consistent Green’s function combined with Hartree NEGF. Authors demonstrate,
for the first time, the slow transition from low-temperature SET behavior to room temperature
MOSFET operation.
A summary of typical device parameters is presented in the Table 2.1. The performances are reported
by authors in different ways and some data are missing.
Device
TABLE 2.1: COMPARISON BETWEEN TYPICAL DEVICE PERFORMANCES.
PADOX SOI
devices
Blockade in
MOSFET
Doped
nanowire
Electrically
induced
SET
GAA wires
This work:
local-SOI
Section 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 4.3
Dot type
Island
capacitance
Tunnel
barriers a
Max I D b
ID peak-tovalley
ratioc Oscillating
V G-range
Si channel
doping
Number of
oscillations
SOI
constriction
SOI
MOSFET
Dopant
atoms
Induced SOI
island
1D
quantization
Induced in
corners
0.1-0.4aF 10.5aF 1.7aF 1.06-3.2aF - 6-16aF
- - variable induced - ~10MΩ
- - 100-400pA 500pA 10nA 10pA
- ~2 decades 1-2 decades >2 decades weak 3 decades
2-6V ~2V >1V ~5V
- - 2x10 19 cm -3 n-type
(phosphorus)
~10
many and
regular
many and
irregular
many and
irregular
500mV
weak
inversion
p-type
10 15 cm -3
a few
irregular
a. Quantum tunnel resistance, extracted by Orthodox theory formalism in the CB mode.
b. Maximum current level in the CB regime (peak-current).
c. Measured in the CB regime.
200mV
weak
inversion
p-type
10 15 cm -3
Wire length 10-35nm 40nm 70-80nm ~40nm 350nm 1-1.2μm
Max CB
temperature
30K 20K
Measured at
T=4.2K only
Oscillations
at T=4.2K
8
~35K 20K
Gate oxide 15-40nm 24nm ~20nm 10nm 4nm 10-20nm
Lithography e-beam e-beam e-beam e-beam phase-shift optical
Reference [Nam03] [Hof05] [Alt03] [Hu04] [Sin06] [Pot06]

Finite element analysis of silicon nanowires 69
2.4 Finite element analysis of silicon nanowires
The silicon nanowire device, as shown in the previous sections, is the key structure for the combined
fabrication of SET and MOS on a same technology platform.
This section proposes finite element simulation and analysis of specific device cross-section shapes
and dimensions. The different simulation tools used 1 are addressing the two following problems:
• Corner effect in triangular device (see Figure 3.43 on page 107)
• Quantization effects in circular cross-section devices (see Figure 3.33 on page 101)
MOSFET simulations only are considered. No Coulomb Blockade code is implemented in the various
scripts we used. However, due to the seamless transition from room temperature MOSFET behavior
to cryogenic temperature SET behavior (see Section 4.3), this analysis serves for a full device
understanding.
2.4.1 Corner effect in triangular cross-section devices
Corner effects in MOS transistor [Sta04] are observed at the proximity of two adjacent gate regions
(See Figure 3.34). Effects such as a higher electric field and a lower threshold voltage V T occur.
Corner effects are mainly influenced by the body doping, the dielectric (gate oxide) thickness, the
geometry (angle of the corner, rounded shape) and the temperature of the silicon lattice.
In the subthreshold region, earlier inversion in the corners than in the edges of the devices are
observed. In some cases, devices show a double threshold voltage or a double peak in the g m -V G
characteristic. This effect is essentially considered as parasitic by many authors!
Corner phenomenon become significant only for high body doping (N A >5x10 18 cm -3 ) and at low
temperature. Indeed, as suggested by the band structure in Figure 2.14, corner effects are higher
when the difference between the Fermi level E F and the valence band E V is reduced.
EF-Ei [eV]
0.6
100
200
Temperature, T [K]
Figure 2.14: Fermi level E F in silicon as a function of temperature for two different acceptor levels.
The Equation 2.1 is the effective density of states in the valence band and serves as input for
Equation 2.2, that should be minimized to enhance corner effects.
Effective density of states in the valence band: NV 2 2πm0 (2.1)
h 2
3 2
⎛ ⋅ ----- ⎞
⎝ ⎠
⁄
=
NV Difference between EF and EV: EF – EV =
kTln⎛------
⎞
(2.2)
⎝N⎠ A
In the Equation 2.1, m 0 stands for the free-electron mass (m 0 =0.91x10 -30 kg) [Sze02].
1. See: http://www.synopsys.com/products/tcad/tcad.html
0
-0.6
Conduction band
Valence band
E C
Ei
EF: NA=10 18 cm -3
EF: NA=10 15 cm -3
EV
300
kT

70 CHAPTER 2: Silicon nanowire for MOS/SET combined functionality
The Table 2.2 summarizes E F -E V values for different temperatures and body doping levels.
TABLE 2.2: E F -E V CALCULATED AS A FUNCTION OF TEMPERATURE AND BODY DOPING.
Temperature
p-type doping
300K 150K 77K
10 15 cm -3 262meV 118meV 53.7meV
10 17 cm -3 143meV 58meV 23.1meV
5x10 18 cm -3 41.7meV 7.41meV ~0
As all our devices integrated by the local-SOI or SOI technology (See Sections 3.4 and 3.5) are lowdoped
(typically 10 15 cm -3 ), we cannot expect a strong impact from corner effects.
Theory and simulation predict that at room temperature and for a doping concentration as high as
N A =5x18cm -3 , the corner current cannot be distinguished from the main current at the edges of the
device. However, at low temperature (typically below 150K) and for a highly doped body, it gets
possible to observe a double peak in both g m -V G and I D -V G characteristics.
The finite element simulation investigated in this work highlights, that even if a double peak of the
g m -V G is not observed, there is still a much higher concentration of minority carriers in the corners.
This higher concentration increases the ON-current in the strong inversion mode. Corner inversion
appears in the subthreshold mode and, in this regime only, a volume inversion is induced in the
corners.
Furthermore, due to quantum distribution at the interface, a darkspace in silicon pushes the
maximum carrier concentration far away from the interfaces (See Section 1.3.4 on page 24). This can
bring substantial enhancement of the carrier mobility by reducing phonon and surface roughness
scattering.
The simulations proposed in the Figures 2.15 to 2.17 show the electron carrier density in low-doped
(N A=10 15 cm -3 ) triangular wires. These cross-section shapes correspond exactly to the cross-section
of a low temperature oscillating device (See Section 4.3.1). Indeed, the role of corners to induce SET
islands in the weak inversion regime is essential.
The triangular cross-section is 45nm x 30nm and the gate oxide thickness is 20nm. We used a
Density-Gradient approach [Con02] in order to partly take into account energy quantization that
exist in such a small cross-section. The Density-Gradient model is discussed in the next section.
Finally, no stress was introduced in the simulation, even if stress in small cross-section has a strong
impact, as demonstrated in the Section 4.2.4.
Figure 2.15: Electron density simulation in a low-doped triangular cross-section, biased in the weak
inversion regime. The two AA’ and BB’ cut lines are displayed on the left picture. No corner effect is
observed, even in the sharper corner AA’.

Finite element analysis of silicon nanowires 71
Figure 2.16: Electron density simulation in a low-doped triangular cross-section, biased at V T =V G .
A significant corner effect is observed, and particularly in the sharper corner AA’, which has a
double electron density compared to an edge interface.
Figure 2.17: Electron density simulation in a low-doped triangular cross-section, biased in the strong
inversion regime. A ratio of about 8 is found in the electron density between the sharpest corner AA’
and an edge interface. This cross-section shape is fully depleted.
A comparison between measurement and simulation is proposed in Figure 2.18. The current is
calculated with Equation 4.7, using a high constant mobility of 800cm 2 /Vs (See Figure 4.12).
Figure 2.18: Simulation and measurement (corresponding to Figure 4.16) of a 1μm long device.

72 CHAPTER 2: Silicon nanowire for MOS/SET combined functionality
The plots in Figure 2.18 deserve the following comments:
•At V D =200mV, this device is still in the linear regime (in strong inversion), as shown in
Figure 4.30. This justifies the Equation 4.7 used to calculate the total drain current in the
device.
• The OFF-current of the real device is about 0.1pA, and is dictated by the SiO 2 /Si
interface quality (charges in the channel). This is not taken into account by the simulator.
• The matching between simulated and measured subthreshold slope and threshold voltage
is pretty good.
• The ON-current of the measured device is higher. This is due to the channel enlargement
at the source and drain sides.
The investigation of corner effects was also done at T=77K on a low-doped (N A =10 15 cm -3 )
triangular cross-section. As predicted by theory, no double peak in the I D -V G characteristic is
observed. Simulation results are given in Figure 2.19.
Figure 2.19: (Left) Log. and lin. scales I D -V G simulation of a 1μm long device, in the strong
inversion regime. At this temperature, an increased mobility of 1500cm 2 /Vs is used, accordingly to
Figure 4.13. No double threshold is observed. (Right) AA’ and BB’ cross-sections through the
device. The difference between corner and edge interfaces is important, compared to room
temperature simulation.
In this section, the role and importance of corners is highlighted. The use of a Density-Gradient
approach, instead of the basic drift-diffusion equations, has also shown how local volume inversion
appears in the corners, when the device is biased in the subthreshold regime. A more details
simulation, based on a coupled Poisson-Schroedinger algorithm, is given in the Section 4.3.2.
2.4.2 Density-Gradient simulation of circular nanowires
The second key simulation we would like to present in this chapter is the strong impact of energy
quantization that appear in highly reduced channel cross-sections. We have observed devices with a
5nm-diameter, as shown in Figure 3.33. In such small cross-sections, the electrons are 2D-quantized
and free along the length of the wire.
The Density-Gradient method was used as a simulation model, and compared with results based on
the Poisson equation only. Density-Gradient theory [Con02] is a device-oriented continuum
description of electron transport that includes lowest-order energy quantization (and not a complete
quantum description, as the Schroedinger equation 1 ).
The Density-Gradient model in the DESSIS 2 simulator is implemented in terms of a partial
differential equation of the Schroedinger equation. Details are beyond the scope of this report.
1. Microscopic theory (Schroedinger) is however not more fundamental or better than a macroscopic approach
(Drift-diffusion). Better depends on one’s applications. They are rather complementary and both useful.
2. See: http://www.synopsys.com/products/tcad/tcad.html

Finite element analysis of silicon nanowires 73
The main advantage of the Density-Gradient, compared with Schroedinger equation, is a much
reduced resolution time and a numerically very robust algorithm.
The first simulation proposed is shown in Figure 2.20. This shows the electron density distribution
across a low-doped 5nm diameter wire. In the strong inversion mode, the two electron density peaks
are so close that a quasi-constant profile appears.
Figure 2.20: Room temperature Density-Gradient simulation of a 5nm silicon diameter device
(N A =10 15 cm -3 ), biased at different voltages. The wire is fully depleted. The gate oxide is 20nm and
highly doped gate-all-around polysilicon (N D =10 20 cm -3 ) is used as a gate electrode.
The same algorithm is used to compute the total electron density integral (see Figure 2.21). Contrary
to Figure 2.18, we do not calculate the total current in the device using Equation 4.7, because of the
uncertainty on the mobility value.
A room temperature measurement of a 5nm diameter device, corresponding to this simulation, is
however proposed in Figure 4.7. The extracted low-field mobility in this device is about 480cm 2 /Vs
and is quite high compared with the extreme width/surface ratio.
Figure 2.21: Log. and lin. characteristics of the electron density integral versus the gate voltage. A
comparison between Poisson only and a coupled Poisson Density-Gradient simulations shows how
energy quantization slightly reduces the electron density in the section.

74 CHAPTER 2: Silicon nanowire for MOS/SET combined functionality
2.5 The SET-NEMS architecture
In this final section, we briefly present a SET-NEMS combined architecture that was originally
proposed in 2003 by EPFL and presented at IEDM [Mah03]. This device architecture is motivated by
the fact, that it allows the compensation of the background charge effect by tuning the value of the
SET gate capacitance. NEMS stands for nano-electro-mechanical systems. The core of the SET-
NEMS device is a silicon nanowire. Above it, we proposed to add a moving electrode that acts as a
second tunable gate.
A 3D sketch of a SET-NEMS device, as well as a channel cross-section, are proposed in Figure 2.22.
No detailed technology fabrication steps are proposed in this chapter. However, such a moving
electrode can be rather simply processed in an above-IC integration platform. A metallic moving
electrode deposited over a sacrificial layer is certainly the most efficient process that can be
considered. The moving electrode is anchored by hinges to the wafer. Many types of design are
possible. In the sketch of Figure 2.22, two fix electrodes are used for the actuation. A voltage
difference applied between fix and moving electrodes results in an attractive electrostatic force. This
mechanism tunes the variable gap t gap between the SET island and the electrode.
Moving
electrode
D
BOX
Si
SiNW
S
Figure 2.22: (Left) Tri-dimensional SET-NEMS geometry on a SOI wafer. A moving MEMS-like
electrode is defined over the silicon nanowire structure and acts as a second tunable gate. (Right)
Cross-section cut showing the double-gate SiNW electrostatic control.
The moving electrode architecture was developed and modelled initially for the integration of
suspended-gate MOSFET (SG-MOSFET), as explained in [Pot01]. SG-MOSFET advanced
modelling - based on design of experiment - is reported in [Ion02]. A relatively high movable
electrode surface (>100μm 2 ), a small air gap (

The SET-NEMS architecture 75
The schematic presented in Figure 2.23 shows an equivalent electrical schematic of a SET-NEMS
device. SET-NEMS is modelled as a double-gate SET. The moving electrode tunes the value of the
gate-to-island C G2 capacitance. The plot in Figure 2.23 is a numerical simulation of the gap distance
t gap and of the tunable capacitance C G2 as a function of V DC . The actuation bias V DC is the quasi-DC
voltage between fix and moving electrodes. For the simulation of the Figure 2.23, we consider an
initial air gap of 100nm. This corresponds to the equilibrium condition. Details are in [Mah03].
From the plot of Figure 2.23, we observe that the tunable NEMS capacitor acts as a two-state
capacitive switch with a pull-in voltage V PI =0.6V. The pull-in voltage corresponds to the applied
voltage at which the movable electrode snaps down. The resulting C G2 capacitance behaves as a twostate
variable capacitance.
By coupling a NEMS tunable capacitor with the Monte Carlo simulator SIMON [Was97], we report
simulated electrical characteristics of an hybrid SET-NEMS architecture. The simulation schematic
is displayed in Figure 2.24. We used the values of C G2 =0aF (gate up) and C G2 =8aF (gate down)
corresponding to the two mechanical states of the moving electrode. The second gate voltage V G2 is
not coupled to the actuation voltage V DC . For this example, V G2 is connected to the ground. The two
resulting I D -V G1 output characteristics, simulated at T=4.2K, are reported in the plot of Figure 2.24.
I D
V DS
C TD
C G2
C G1
V G1
C TS
V G2
Figure 2.24: (Left) SIMON [Was97] equivalent circuit schematic of a SET-NEMS device. (Right)
Low temperature I D -V G1 simulated characteristics for a gate up (C G2 =0) and for a gate down
(C G2 =8aF). V G2 is connected to the ground and V DS =10mV.
Applications of such an exceptional device are in its new functions. For example, the tunable second
gate can be used to cancel random charge fluctuations that usually shift I D -V G characteristics in
single-gate SET. This can also serve to build a dual oscillation period SET. The device period is
either ΔV G1 =e/C G1 or ΔV G2 =e/C G2 , depending on the controlled gate. If properly buffered with
MOS transistors, then tunable oscillating characteristics may also be used for applications as (i)
threshold gate, (ii) high-density neural networks or (iii) arrays of analog-to-digital converters. Many
low power applications are successfully addressed with SET-NEMS devices, even if a strong
technological effort is needed. The large electrodes needed for actuation are currently a major issue.
Further developments of SG-MOSFET and SET-NEMS architectures have been very recently
proposed. A group from the Tokyo Institute of Technology has published a very valuable report
[Pru07]. In this paper, a nanowire SET is combined with a movable electrode and show interesting
results by combining orthodox theory and NEMS modelling.
A joint collaboration between EPFL and Stanford University 1 has also resulted in a remarkable work
on SG-MOSFET devices [Tsa07]. Authors propose, for the first time, a hybrid numerical simulation
approach combining ANSYS 2 and DESSIS 3 in a self-consistent finite element analysis. This
compact modelling - including both micro-electro-mechanical and the solid-state domain in a single
simulation loop - is a highly challenging task.
1. See: https://www.stanford.edu/group/nanoelectronics/index.htm
2. See: http://www.ansys.com/
3. See: http://www.synopsys.com/products/tcad/tcad.html
Drain current, I D [nA]
25
20
15
10
5
0
C G2 =0
C G2 =8aF
T=4.2K
V =10mV
DS
C =C =2aF
TD TS
R =R =100kΩ
TD TS
C =4aF
G1
0 20 40 60 80 100
Gate Voltage, V [mV]
G1

76 CHAPTER 2: Silicon nanowire for MOS/SET combined functionality
2.6 Summary
2.6.1 Synopsis
We proposed the following in this chapter:
• We clearly demonstrate how a silicon nanowire can serve as a combined structure for
both MOS and SET operating modes.
• We also show that Si/SiO 2 is the major platform for the integration at nano-scale of
single electron devices.
• Among many technologies reported in the literature, the PADOX process is currently the
most efficient way to create single electron islands in silicon nanowires.
• It was observed a huge gap between the theory reported by the classical SET modeling
described by Orthodox Theory and the different device architectures published, that does
not fit with this model. This discrepancy is due to the fact, that the Orthodox Theory
considers ideal islands (metallic) and barriers (dielectric) and is not adapted for
semiconductor-based SET.
• The physical origin of the SET island(s) and tunnel barriers is dependent from the
integration technology used. It was proved that a continuous constricted silicon
nanowire, with a high strain level in its central part, can act as a barrier-island-barrier
electronic structure.
• Performances of the reported works are compared. Our original contribution, based on a
local-SOI architecture has some key advantages compared with state-of-the-art papers.
We measured a 3 decades peak-to-valley SET current, we extracted 6-16aF island
capacitance and we show a maximum SET operating temperature of 20K.
• Finite element analysis of silicon nanowires is proposed. This emphasizes first the role of
corners in silicon nanowires, and second this shows what is the real impact of energy
quantization in nano-scale cross-sections structures.
• Finally, the SET-NEMS architecture, originally proposed by EPFL in 2003, is reported
and briefly analyzed. This device has the unique advantage to compensate the
background charge effect that randomly shifts the I D -V G phase in all Coulomb Blockade
devices.

Bibliography 77
2.7 Bibliography
[Alt03] T. Altebaeumer and H. Ahmed, ’’Tunnel barrier formation in silicon nanowires’’, Japanese Journal
of Applied Physics, vol. 40, pp. 414-417, 2003.
[Aug00] R. Augke, W. Eberhardt, C. Single, F. E. Prins, D. A. Wharam and D. P. Kern, ’’Doped silicon single
electron transistors with single island characteristics’’, Applied Physics Letters, vol. 76 (15), pp.
2065-2067, 2000.
[Aus97] D. G. Austing, T. Honda and S. Tarucha, ’’Vertical single electron transistors with separate gates’’,
Japanese Journal of Applied Physics, vol. 36, pp. 4151-4155, 1997.
[Boe03] F. Boeuf, X. Jehl, M. Sanquer and T. Skotnicki, ’’Controlled single-electron effects in
nonoverlapped ultra-short silicon field effect transistors’’, IEEE Transactions on Nanotechnology,
vol. 2 (3), pp. 144-148, 2006.
[Col06] J.-P. Colinge, A. J. Quinn, L. Floyd, G. Redmond, J. C. Alderman, W. Xiong, C. R. Cleavelin, T.
Schulz, K. Schruefer, G. Knoblinger and P. Patruno, ’’Low-temperature electron mobility in trigate
SOI MOSFETs’’, IEEE Electron Device Letters, vol. 27 (2), pp. 120-122, 2006.
[Con02] D. Connelly, Z. Yu and D. Yergeau, ’’Macroscopic simulation of quantum mechanical effects in 2-D
MOS devices via the density gradient method’’, IEEE Transactions on Electron Devices, vol. 49 (4),
pp. 619-626, 2002.
[Cui00] Y. Cui, X. Duan, J. Hu and C. M. Lieber, ’’Doping and electrical transport in silicon nanowires’’,
Journal of Physical Chemistry B, vol. 104 (22), pp. 5213-5216, 2000.
[Eva01] G. J. Evans, H. Mizuta and H. Ahmed, ’’Modelling of structural and threshold voltage characteristics
of randomly doped silicon nanowires in the Coulomb-blockade regime’’, Japanese Journal of
Applied Physics, vol. 40, pp. 5837-5840, 2001.
[Hof05] M. Hofheinz, X. Jehl, M. Sanquer, G. Molas, M. Vinet and S. Deleonibus, ’’Detection of individual
traps in silicon nanowire transistors’’, Proceedings of ESSDERC, pp. 225-228, Grenoble FR, 2005.
[Hor01] S. Horiguchi, M. Nagase, K. Shiraishi, H. Kageshima, Y. Takahashi and K. Murase, ’’Mechanism of
potential profile formation in silicon single-electron transistors fabricated using pattern-dependent
oxidation’’, Japanese Journal of Applied Physics, vol. 40, pp. 29-32, 2002.
[Hu04] S.-F. Hu, Y.-C. Wu, C.-L. Sung, C.-Y. Chang and T.-Y. Huang, ’’A dual-gate-controlled singleelectron
transistor using self-aligned polysilicon sidewall spacer gates on silicon-on-insulator
nanowire’’, IEEE Transactions on Nanotechnology, vol. 3 (1), pp. 93-97, 2004.
[Ind07] K. M. Indlekofer, J. Knoch and J. Appenzeller, ’’Understanding Coulomb effects in nanoscale
Schottky-Barrier-FETs’’, Transactions on Electron Devices, vol. 54 (6), 2007.
[Ion02] A. M. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M. Declercq, P. Renaud, C. Hibert, P. Fluckiger and
G. A. Racine, ’’Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG-
MOSFET) with a metal-over-gate architecture’’, Proceedings of ISQED, pp. 496-501, San Jose CA,
2002.
[Ish97] H. Ishikuro and T. Hiramoto, ’’Quantum mechanical effects in the silicon quantum dot in a singleelectron
transistor’’, Applied Physics Letters, vol. 71 (25), pp. 3691-3693, 1997.
[Jeh03] X. Jehl, M. Sanquer, G. Bertrand, G. Guégan, S. Deleonibus and D. Fraboulet, ’’Silicon single
electron transistors with SOI and MOSFET structures: the role of access resistances’’, IEEE
Transactions on Nanotechnology, vol. 2 (4), pp. 308-313, 2003.
[Kim01] D. H. Kim, S.-K. Sung, K. R. Kim, B. H. Choi, S. W. Hwang, D. Ahn, J. D. Lee and B.-G. Park, ’’Si
single-electron transistors with sidewall depletion gates and their application to dynamic singleelectron
transistor logic’’, Technical Digest of IEDM, pp. 151-154, Washington DC, 2001.
[Lee06] W. Lee, P. Su, H.-Y. Chen, C.-Y. Chang, K.-W. Su, S. Liu and F.-L. Yang, ’’An assessment of singleelectron
effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide in near room temperature’’,
IEEE Electron Device Letters, vol. 27 (3), pp. 182-184, 2006.
[Mah03] S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. W. Tringe, Y. Leblebici, M. Declercq,
K. Banerjee and A. M. Ionescu, ’’SETMOS: A novel true hybrid SET-CMOS high current Coulomb
Blockade oscillation cell for future nano-scale analog ICs’’, Technical Digest of IEDM, pp. 29.7.1-
29.7.4, Washington DC, 2003.
[Mat97] K. Matsumoto, ’’STM/AFM nano-oxidation process to room-temperature-operated single-electron
transistor and other devices’’, Proceedings of the IEEE, vol. 85 (4), pp. 612-628, 1997.

78 CHAPTER 2: Silicon nanowire for MOS/SET combined functionality
[Mil96] A. A. Mills, S. Day and S. Parkes, ’’Mechanics of the sandglass’’, European Journal of Physics, vol.
17, pp. 97-109, 1996.
[Mon03] S. Monfray, A. Souifi, F. Boeuf, C. Ortolland, A. Poncet, L. Militaru, D. Chanemougame and T.
Skotnicki, ’’Coulomb-blockade in nanometric Si-film silicon-on-nothing (SON) MOSFETs’’, IEEE
Transactions on Nanotechnology, vol. 2 (4), pp. 295-300, 2003.
[Mor01] N. Y. Morgan, D. Abusch-Magder, M. A. Kastner, Y. Takahashi, H. Tamura and K. Murase,
’’Evidence for activated conduction in a single electron transistor’’, Journal of Applied Physics, vol.
89 (1), pp. 410-419, 2001.
[Nam03] H. Namatsu, Y. Watanabe, K. Yamazaki, T. Yamaguchi, M. Nagase, Y. Ono, A. Fujiwara and S.
Horiguchi, ’’Fabrication of Si single-electron transistors with precise dimensions by electron-beam
nanolithography’’, Journal of Vacuum Science and Technology B, vol. 21 (1), pp. 1-5, 2003.
[Nis04] K. Nishiguchi, H. Inokawa, Y. Ono, A. Fujiwara and Y. Takahashi, ’’Automatic control of oscillation
phase of a single-electron transistor’’, IEEE Electron Device Letters, vol. 25 (1), pp. 31-33, 2004.
[Pot01] V. Pott, A. M. Ionescu, R. Fritschi, C. Hibert, P. Fluckiger, M. Declercq, P. Renaud, A. Rusu, D.
Dobrescu and L. Dobrescu, ’’The suspended-gate MOSFET (SG-MOSFET): a modeling outlook for
the design of RF MEMS switches and tunable capacitors’’, CAS Conference, vol. 1, pp. 137-140,
Sinaia RO, 2001.
[Pot06] V. Pott, D. Bouvet, J. Boucart, L. Tschuor, K. E. Moselund and A. M. Ionescu, ’’Low temperature
single electron characteristics in gate-all-around MOSFETs’’, Proceedings of ESSDERC, pp. 427-
430, Montreux CH, 2006.
[Pru07] B. Pruvost, H. Mizuta and S. Oda, ’’3-D design and analysis of functional NEMS-gate MOSFETs
and SETs’’, IEEE Transactions on Nanotechnology, vol. 6 (2), pp. 218-224, 2007.
[Sai01] M. Saitoh, N. Takahashi, H. Ishikuro and T. Hiramoto, ’’Large electron addition energy above
250meV in a silicon quantum dot in a single-electron transistor’’, Japanese Journal of Applied
Physics, vol. 40, pp. 2010-2012, 2001.
[Shi00] K. Shiraishi, M. Nagase, S. Horiguchi, H. Kageshima, M. Uematsu, Y. Takahashi and K. Murase,
’’Designing of silicon effective quantum dots by using the oxidation-induced strain: a theoretical
approach’’, Physica E: Low-dimensional Systems and Nanostructures, vol. 7 (3-4), pp. 337-341,
2000.
[Sin06] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, C. H. Tung, K. M. Hoe, S.
R. Omampuliyur, D. Tripathi, A. O. Adeyeye, G. Q. Lo, N. Balasubramanian and D. L. Kwong,
’’Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channelorientation
and low temperature on device performance’’, Technical Digest of IEDM, pp. 1-4, San
Francisco CA, 2006.
[Sta04] M. Stadele, R. J. Luyken, M. Roosz, M. Specht, W. Rosner, L. Dreeskomfeld, J. Hartwich, F.
Hofmann, J. Kretz, E. Landgraf and L. Risch, ’’A comprehensive study of corner effects in tri-gate
transistors’’, Proceedings of ESSDERC, pp. 165-168, Leuven BE, 2004.
[Sze02] S. M. Sze, ’’Semiconductor devices: Physics and Technology’’, John Wiley, New-York NY, 2002.
[Tak96] Y. Takahashi, H. Namatsu, K. Kurihara, K. Iwadate, M. Nagase and K. Murase, ’’Size dependence
of the characteristics of Si single-electron transistors on SIMOX substrates’’, IEEE Transactions on
Electron Devices, vol. 43 (8), pp. 1213-1217, 1996.
[Tak02] Y. Takahashi, Y. Ono, A. Fujiwara and H. Inokawa, ’’Silicon single-electron devices’’, Journal of
Physics: Condensed Matter, vol. 14 (39), pp. 995-1033, 2002.
[Til01] A. Tilke, R. H. Blick, H. Lorenz and J. P. Kotthaus, ’’Single-electron tunneling in highly doped
silicon nanowires in a dual-gate configuration’’, Journal of Applied Physics, vol. 89 (12), pp. 8159-
8162, 2001.
[Til03] A. Tilke, F. C. Simmel, H. Lorenz, R. H. Blick and J. P. Kotthaus, ’’Quantum interference in a onedimensional
silicon nanowire’’, Physical Review B, vol. 68, pp. 075311 1-6, 2003.
[Tsa07] D. Tsamados, Y. S. Chauhan, C. Eggimann, K. Akarvardar, H.-S. P. Wong and A. M. Ionescu,
’’Numerical and analytical simulations of suspended Gate - FET for ultra-low power inverters’’,
Proceedings of ESSDERC, pp. 167-170, Munich DE, 2007.
[Was97] C. Wasshuber, H. Kosina and S. Selberherr, ’’SIMON: a simulator for single-electron tunnel devices
and circuits’’, IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems,
vol. 16, pp. 937-944, 1997.
[Was05] R. Waser (Editor), ’’Nanoelectronics and information technology’’, Wiley-VCH Verlag, Weinheim
DE, 2005.

Chapter 3
Hybrid SET/MOS technology
This third chapter describes in details all the original techniques developed for the realization of
silicon nanowires. Each section includes ideas, process flow, design and devices observation. The
integration was performed at the EPFL Center of Micro-Nanotechnology (CMI) on 4’’ wafers,
excepted for some specific steps, where collaborations with academic and industrial partners was
organized.
This chapter starts with a brief introduction on the role of lithographic tools to obtain nano-scale
devices. Other sections are on the successive process developed during this work. Four original
techniques have been considered and analyzed. The first one is the Lateral Pattern Techniques
(LPD), the second is on Focused Ion Beam (FIB) direct prototyping. Basic characterization of
obtained devices are shown, even if none of these two first technologies have proved enough
reliability to deserve future investigations.
Then, a local-SOI and a pure SOI top-down silicon wire technology were developed and successfully
integrated. These two technologies, which represent the technological core of this thesis, have been
reported in various Conferences and Journals.
The complete device characterization is proposed in the Chapter 4. Finally, this chapter is concluded
with an essential discussion on the scalability of the local-SOI and SOI technologies.

80 CHAPTER 3: Hybrid SET/MOS technology
3.1 The smaller, the better
The key point of this chapter is the extremely small resolution that must be achieved in silicon
nanowire technology. The planar resolution is given preliminary by the lithography, and second by
any process tricks (etching, oxidation) that helps to reduce planar dimensions.
The lithography is the technological definition of 2D patterns on the surface of the wafer. In CMOS
industry, the lithography is now a subject of big concern. Resolution improvement for high speed,
high reliability and low cost lithography is a true challenge. The ITRS reports a roadmap for
lithography [Lit06]. CMOS industry is mainly using projection (stepper) optical lithography, with
manufacturable solutions known down to 60nm. For further technology nodes (45nm and below), no
solutions are known, even if these smaller nodes are supposed to be introduced in production in
2008. Solutions as extreme UV, projection lithography or imprint are currently developed.
An interesting report was proposed at IEDM 2005 by B. Lin [Lin05]. The author presents
unprecedented difficulties that lithography is facing now, as well as solutions to handle small CMOS
nodes. The paper [Ito00], published in Nature, also highlights main challenges of optical lithography,
and discussed both optical and non-optical high-resolution lithographic systems.
For this thesis report, we worked with many different lithographic tools. However, we were
dependent from EPFL facilities. The lithography is consuming a large percentage of the cleanroom
process time, and any collaborations with external partners is not realistic for all levels of integration.
A single electron island should be as small as a few nanometers. There is currently no systems that
allow a large scale integration of single electron devices. Figure 3.1 represents, at the same scale, all
lithographic systems we considered during this work. The main limitation is the EPFL
photolithographic system 1 , with a weak resolution of 0.8μm only. This resolution is not good
enough, compared with the target 2 . In terms of dimensions, the ratio between the EPFL
photolithographic system and expected SET dimensions is more than 100.
0.8μm
The smallest pattern
achievable with EPFL
photolithography:
0.8μm x 0.8μm
0.8μm
330nm
Typical
stepper
lithography
pattern
330nm
Lateral pattern defined
(LPD) lithography
Figure 3.1: Different lithographic patterns plotted at the same scale. The largest square on the left
shows the best achievable photolithography with EPFL system. A single electron island should be
typically smaller than 5nm in order to operate at a reasonable high temperature. In between, are
shown different types of lithography we considered during this work.
The highest resolution system is given by the electron beam (e-beam) lithography. Unfortunately,
EPFL has currently no e-beam facilities 3 and we had no choice that to develop smart lithography to
go beyond the resolutions shown in Figure 3.1.
Excepted critical dimensions, other lithographic considerations have to be checked. This includes:
writing speed and writing density, alignment to other levels, impact of topography and underlying
layers, on-wafer reproducibility, chemistry and polarity of the resist and global cost per device.
1. Heidelberg DWL200 Laser Writer. See: http://cmi.epfl.ch/photo/home_photo.html
2. Defining SET with photolithographic tools is like asking Michelangelo to sculpt David with a pneumatic drill.
3. A new EPFL e-beam system - Vistec EBPG5000 - is now available and in operation since September 2007.
See: http://cmi.epfl.ch/nanotools/VistecEBPG5000/VistecEBPG5000_introduction.html
0.8μm
FIB E-beam SET island
70nm 20nm 10nm

Lateral Pattern Definition (LPD) technique 81
3.2 Lateral Pattern Definition (LPD) technique
In this section, we describe a technique used for the definition of nano-scale silicon nanowires. This
non-lithographic process is called Lateral Pattern Definition (LPD). This consists of transferring
lateral side-walls into a planar hard mask, the planar dimension being defined by the side-wall
material thickness. This side-wall can be technologically done by an oxide growth or by any
conformal deposition. The principle of a LPD process are shown in Figure 3.2.
Sacrificial
layer
Figure 3.2: Principle of the lateral pattern definition. Different materials, deposition and etch can be
considered. The LPD layer thickness t LPD is transferred into a planar dimension.
The unique advantage of this technique is the possibility to obtain nano dimensions in a planar
dimension, without using any lithographic tool. However, this technique is rather difficult to control
at nano-scale and the contacting of a LPD-defined nanowire is really challenging. Table 3.1 presents
a summary of LPD key advantages and limitations.
+
+
+
+
+
+
+
+
+
LPD layer
Substrate
t LPD
Anisotropic etch
TABLE 3.1: ADVANTAGES AND LIMITATIONS SUMMARY OF A LPD PROCESS.
Advantages Limitations
Non-lithographic
Ultra low-cost
Fast and full wafer process
Hard mask for line transfer
Excellent yield and on-wafer
reproducibility
Scalability as good as e-beam lithography
(below 10nm)
Excellent for long nano-lines, or cross-bar
circuits
Double density process: one pattern results
in two wires
Double LPD process: one pattern results in
four lines
Three original LPD techniques have been developed for the fabrication of nanowires (See Sections
3.2.1 to 3.2.3). They all have advantages or limitations, but unfortunately none of them has resulted
in an efficient and stable process for devices integration. The limitations we have faced are
essentially resulting from poor etch facilities (roughness, selectivity), and it was decided not to
continue with this technology. However, we are convinced that the simplicity of this technique could
have a very strong impact for the rapid fabrication of nanowire lattices and arrays.
Concerning the literature, there are surprisingly only few papers on LPD techniques. Furthermore,
there is no uniformity in LPD reports. This process is named by many different ways, as lateral
pattern definition, sidewall process, spacer defined patterning, edge transfer, nanowire lattices, etc.
Key examples are presented in the next page.
-
-
-
-
-
-
-
-
-
-
Sacrificial
layer removal
t LPD
Pattern transfer
t LPD
Difficult to be integrated in a process flow
Can be used once in a process, and usually
at the beginning
Particular layout needed
Much more integration steps
Excellent etch facilities needed (selectivity,
anisotropy)
Only lines can be defined (and not full nano
geometries)
Difficult to take contacts on wires
The inverted contrast (nano-gap) is even
more difficult
Highly sensitive to material and etch
roughness
High temperature process (oxidation,
LPCVD)

82 CHAPTER 3: Hybrid SET/MOS technology
Integration processes exploiting LPD techniques have all been published recently. In terms of
applications, the main driver is certainly the FinFET geometry (and particularly multi-finger fins) as
explained in section 1.4.2. The need of advanced lithography for large area integration has pushed
engineers to develop non-lithographic process.
LPD-based FinFET devices are reported at the same time by the Inter-University Microelectronics
Center, Leuven, BE [Ani03], and by UC Berkeley [Cho02]-[Cho03]. The paper [Cho02] proposes
SiGe as a sacrificial material and phospho-silicate glass (PSG) as LPD layer. P-type MOSFET
characteristics of L G =30nm are shown. Further scaling and improvement are described in [Cho03].
D S
Figure 3.3: Four SOI fin structures defined by
spacer deposition and transfer. Picture by
[Deg07], published in 2007.
The most recent application of LPD process for
FinFET integration is proposed by IMEC, under
the reference [Deg07]. Authors obtain fin
structures as small as 20nm in width, with a
25nm pitch. Figure 3.3 is a SEM picture of 4
SOI fins in parallel connected to two pads,
acting as drain and source.
The process flow developed is a double-LPD
technique. First, LPD SiN spacers are defined
all-around a SiGe structure. Then, the two
resulting lines are used again as sacrificial
material, with TEOS deposition as a second
LPD material. Fins obtained are further partly
oxidized to reduce their widths and to remove
etch damage. Smallest fins width are 13nm,
with a uniform distribution all over the wafer.
The two next examples are not specifically developed for FinFET applications:
200nm
SOI Fin
50nm
SiO 2 spacer
Quartz
substrate
Figure 3.4: A LPD-defined 40nm wide SiO 2
line on a quartz substrate. Picture by [Gra04].
500nm
Figure 3.5: Suspended platinum wires, 20nm in
diameter. Picture by [Mel03].
The Institute of Electron Technology, from
Warsaw PO, has developed a strong activity on
LPD techniques.
In 2004, it was reported in [Gra04] a fabrication
technique for the definition of nano-width lines
on nano-imprint templates. Silicon-on-quartz
patterns are oxidized to produce SiO 2 spacer
line on a quartz template, as shown in Figure
3.4. A scalability of 20nm in lines width has
been demonstrated.
In 2006, the same group has further developed
this technology, inc. the use of polySi and
mono-Si as sacrificial material [Zab06]. This
latest report includes AFM measurement and
stress calculation of oxide nano-fences.
The fabrication technique proposed by Caltech
is based on translating thin film growth
thickness into planar wire arrays [Mel03].
GaAs/AlGaAs superlattices are grown on a
template, then AlGaAs is selectively etched on
the sides. A metal layer is deposited on the
master template and the wire lattice is stamped
on a second wafer (imprinting).
The minimum nanowire diameter measured is
8nm, with a 16nm wire pitch, as seen in Figure
3.5. Easy processing and template multiple-use
are specific advantages of this method.

Lateral Pattern Definition (LPD) technique 83
3.2.1 Polysilicon oxidation LPD process
The first LPD process we tested is based on the oxidation of a sacrificial polysilicon layer.
This process is presented in Figure 3.6, showing the formation of a basic SOI nanowire connected
between two larger pads. The thicknesses of the layers are not shown, this will be discussed later.
The process flow presented in Figure 3.6 does not include all steps for the fabrication of a silicon
nanowire. For example, the thickness of the SOI layer should be first thinned down in the wire part.
Moreover, the gate stack process (GAA) has also to be carefully predicted.
SOI
BOX
(a) (b)
Silicon
substrate
PolySi
Figure 3.6: Polysilicon oxidation LPD process flow on a SOI wafer. (a) LPCVD SiN and PolySi
deposition. (b) Photolithography and PolySi etch. (c) PolySi oxidation. (d) Anisotropic SiO 2 etch,
spacer formation. (e) PolySi release by a dry isotropic etch. (f) Anisotropic nitride etch. (g)
Photolithography. (h) Nano-line partial etch, resist removal. (i) Pads photolithography. (j) SOI
anisotropic etch, resist and hard mask removal, partial BOX etch (depending on the hard mask
removal chemistry).
SiN
(c) (d)
PolySi
oxidation
(e)
PolySi release
(g)
Photolithography
SiO 2
SiO etch: 2
spacer formation
(f)
(h)
(i) Photoresist
(j)
Photolithography
Photoresist
Anisotropic
SiN etch
PolySi
SiO 2 + SiN release
PolySi pattern etch
SiO 2 spacers
Nano-line hard
mask
BOX partly
etched
SOI etch
Resist + hard mask release

84 CHAPTER 3: Hybrid SET/MOS technology
We tested different polysilicon oxidation LPD process on bulk silicon wafers (and not on SOI, in
order to save wafers). We used a fluorine based plasma reactor 1 to etch the different layers. Process
parameters, corresponding to Figure 3.6, are the following:
• Silicon nitride thickness: 150nm
• Polysilicon thickness: 250nm
• LPD oxide growth: 70nm
• Polysilicon etch: Anisotropic SF 6 +C 4 F 8 plasma Figure 3.6 (b)
• Oxide etch: Anisotropic C 2 F 6 plasma Figure 3.6 (d)
• Polysilicon release: Isotropic SF 6 plasma Figure 3.6 (e)
• Nitride etch: Anisotropic C 2 F 6 plasma Figure 3.6 (f)
• Oxide + nitride release: Wet etch (HF 49%) Figure 3.6 (h)
• Silicon etch: Anisotropic SF 6 +C 4 F 8 plasma Figure 3.6 (j)
• Oxide + nitride final release: Wet etch (HF 49%) Figure 3.6 (j)
SiN
70nm
200nm
Si wall 200nm
Si bulk
(a) (b) (c)
Figure 3.7: Polysilicon LPD test structure. (a) Nano-wall etched, with SiN as hard mask. (b) Hard
mask released. (c) Top view of a released nano-wall.
We deduced from this test that the LPD process we proposed is functional, but the choice of oxidized
polysilicon as spacer is not optimal due to polysilicon roughness. The oxidation is done at a
temperature ranging from T=950°C to T=1000°C under a dry O 2 atmosphere. This type of oxidation
is highly controllable, but leads to unavoidable spacers roughness.
However, we also observed that the oxide growth dimension is transferred into a lateral dimension
with a pretty good control of dimensions and with an excellent on-wafer reproducibility.
In spite of this LPD proof of concept was successful, we decided nevertheless to stop polysilicon
oxidation and either to explore silicon oxidation, because of the excessive roughness.
3.2.2 Silicon oxidation LPD process
Si wall
The silicon oxidation LPD process we developed in reported in [Pot05]. The very simple process is
described in Figure 3.8. The process steps are fully simulated using 2D TCAD tools 2 .
SiO2 10nm Photoresist SiO2 70nm
1μm
Silicon
Anisotropic dry etch
Silicon etch
Figure 3.8: The silicon oxidation LPD process.(a) 10nm oxide growth and photolithography. (b)
Silicon anisotropic etch (~250nm) and 70nm oxide growth. (c) Oxide anisotropic dry etch. (d)
Silicon anisotropic dry etch. (e) Oxide wet etch (BHF) removal.
1. Alcatel 601E plasma reactor. See: http://cmi.epfl.ch/
2. Synopsys ISE-TCAD, Dios tool, release 10.0. See: http://www.synopsys.com/products/tcad/tcad.html
200nm
Oxide release
Silicon
nano-wall
(a) (b) (c) (d) (e)
70nm

Lateral Pattern Definition (LPD) technique 85
Results of the silicon oxidation LPD test are proposed in Figure 3.9.
(a)
SiO 2
Figure 3.9: SEM pictures of the silicon oxidation LPD process. (a) Top-view SEM picture
corresponding to the Figure 3.8c. (b) Tilted-view SEM picture of a release silicon nano-wall,
corresponding to the Figure 3.8e.
We observed by SEM imaging that the width of the nano-wall after processing corresponds to the
oxide layer growth. In the test we made, the width is 70nm. In comparison with polysilicon oxidation
LPD patterns (Figure 3.7), the sides roughness has been considerably reduced.
However, this test is only a first step for the integration of silicon nanowire devices. The nano-wall
process needs (i) to be contacted to S/D pads (ii) to have its size reduced and (iii) to be electrically
disconnected from the bulk wafer.
An oxide growth under O 2 atmosphere at T=1050°C was simulated and then performed on a test
wafer. Then, this wafer was cleaved and we observed the oxidized nano-wall corresponding to the
Figure 3.10. As calibrated by process simulation, we see a silicon nanowire embedded in oxide. The
wire has a quasi-circular shape, with about 15nm as diameter. This result is extremely interesting and
was obtained with a 0.8μm resolution photolithography.
65nm SiO 2
200nm
Figure 3.10: SEM picture of an oxidized nano-wall defined by silicon oxidation LPD process. An
insulated silicon nano-wire in the top part of the wire is observed.
Simulation of the oxidation process
Si
Si
Si substrate
200nm
Si nano-wall
Prior to oxidize the wafer, we made a careful 2D process simulation. We used a non-linear viscoelastic
model of oxide growth. This rigorous modeling of oxidation includes chemical reactions at
interfaces, thermal expansion, stress-dependent and crystal orientation dependent oxidation.
The visco-elastic modelling of silicon oxidation is now considered as the most precise approach,
separating the oxide growth into a deviatoric part (viscous) and a dilational part (elastic). Details of
finite elements computation is beyond the scope of this work, and this can for example be found in
the detailed report proposed by Garikipati and Rao in [Gar01]. The Synopsys 1 help file is also
describing the visco-elastic algorithm implemented.
1. Synopsys ISE-TCAD, Dios tool, release 10.0. See: http://www.synopsys.com/products/tcad/tcad.html
(b)
Oxidized wire
Insulated Si wire
Diameter: ~15nm

86 CHAPTER 3: Hybrid SET/MOS technology
A Deal-Grove model of oxide growth is used.
In order to take into account visco-elastic effects, the reaction rate k and the diffusivity D of oxygen
in SiO 2 are affected by mechanical quantities the following:
σn ⋅ VK
k( σn, T)
= k ⎛
0 min⎛1, exp⎛-----------------
⎞⎞⎞
⎝ ⎝ ⎝ kBT ⎠⎠⎠
p ⋅ VD
D( σkk, T)
= D ⎛
0 min⎛1, exp⎛–
--------------- ⎞⎞⎞
⎝ ⎝ ⎝ kBT ⎠⎠⎠
In Equation (3.1), k 0 is the stress free reaction rate, σ n the normal stress acting onto the Si/SiO 2
interface (σ n >0 means tensile stress and σ n

Lateral Pattern Definition (LPD) technique 87
The silicon oxidation LPD S/D pads integration
The next step in the silicon oxidation LPD process consists in contacting the silicon nanowire
between two pads in a true 3D device geometry. We developed and published [Pot05] the following
process flow. This is presented on a SOI wafer, but this can also be considered for bulk silicon wafer
if proper wire oxidation is performed to disconnect it from the bulk.
(a) Gap (

88 CHAPTER 3: Hybrid SET/MOS technology
200nm Si pad 200nm 200nm
Si SiO 2
Figure 3.13: 3D integration of the silicon oxidation LPD process on bulk silicon. (a) Structure with
SiO 2 hard mask, corresponding to Figure 3.12e. (b) Device with oxide release and parasitic gap. (c)
Functional wire, showing however a reduced wire width at S/D connections.
The full wafer device integration remains problematic. Furthermore, the observed silicon roughness
is weak.
The parasitic gaps between S/D and the wire in Figure 3.13b are resulting from a fuzzy effect that
was understood only by process simulation. Again, this proves how LPD process integration can be
tricky.
Figure 3.14: The origin of parasitic gap in silicon oxidation LPD process. On the same cross section
is shown what should be a correct process (on the left) and the wrong one (on the right).
At that point, it seems that the scalability of this process for device integration is limited, mainly due
to 3D un-controlled integration effects and unsatisfactory etch results (surface roughness, etching
notch, only fast etch rate available, no HBr plasma).
Again, we decided not to put a maximum of effort in this process and to focus on other integration
process flows.
3.2.3 Nitride LPD nanowires
The last LPD process we checked is different from polysilicon and silicon oxidation. As the 3D
integration seems difficult, we found a process where a suspended LPD-defined nitride nanowire is
integrated and used as hard mask. This process has a reduced number of integration steps.
The fabrication principle is presented in Figure 3.15.
D S D S
Si
(a) (b) (c)
Anisotropic
Anisotropic
+ Isotropic
SiO2 etch
SiO2 (a)
etch Anisotropic Si etch
(b) (c)
LPD oxide growth
A better
solution
SiO2
what we did
Si substrate
(d) LPD oxide anisotropic etch
(e)
Silicon anisotropic etch
(f)
Hard mask release
OK Parasitic gaps

Lateral Pattern Definition (LPD) technique 89
Silicon
SiO 2
Anisotropic etch
LPCVD SiN SiO2 release
Figure 3.15: The suspended nitride LPD process. An LPCVD low-stress silicon nitride (SiN) is
deposited and further anisotropically etched in a dry etch plasma reactor. The nitride sidewall is
released in a BHF bath, resulting in a suspended nitride nanowire.
The SEM pictures obtained with this process are shown in Figure 3.16.
(a) (b)
SiO 2
SiN Suspended
SiN wire
1μm 1μm
(c) Si
(d)
Suspended
SiN wires
1μm
SiO 2
Suspended
SiN wire
1μm
Etched
Si line
SiO 2
Figure 3.16: SEM pictures of nitride nanowires obtained by LPD integration. (a+b) Tilted view of
partly released nitride nanowires. The anchor is a grown oxide layer. (c) Top view SEM image of
twin SiN nanowires anchored on two oxide lines. The nitride wires width is about 70nm. (d) Etched
silicon line after anisotropic silicon dry etch.
This process was done in a very short time. The negative result is the dreadful etch transfer when
using suspended nitride nanowire as hard mask. However, this process is very easy and fast, and we
proved a scalability down to 70nm.
Many smart use of suspended wires can be considered. For example, we can coat such nanowires
with conductive material and obtain conductive nanotubes! We can also use such small structures in
MEMS/NEMS integration.
Si

90 CHAPTER 3: Hybrid SET/MOS technology
3.3 Focused ion beam prototyping
3.3.1 Introduction to focused ion beam
A Focused Ion Beam (FIB) is a micro-machining tool used for analysis and devices rapid
prototyping. The beam is generated from the ionization of a liquid-metal source (mainly gallium
ions), then ions are accelerated with a field emission tip and focused on the surface of the sample.
Ions are accelerated at an energy ranging from 5 to 50keV.
adsorbate
e -
Ga + beam
atom
target
Figure 3.17: Ion-solid interaction.
Typical applications of FIB processing include [Orl03]:
• Cross-section for multiple layer devices study
• TEM sample preparation
• Local material deposition
• Preferential removal of material
• Semiconductor circuits editing or modifications and mask repair
• Device prototyping
For the prototyping of SET, we used the CMI-EPFL system 1 . Typical performances of such an
equipment are [Fei07]:
• Electron and ion column mounted at 52° to each other.
• Electron beam voltage: 200V to 30kV, continuously adjustable.
• Electron beam current < 20nA.
• Electron beam resolution: 1.1nm @ 15kV, 2.5nm @ 1kV.
• Electron detection: in-lens secondary electrons (SE) and back scattered electrons (BSE).
• Ion beam voltage: 5kV to 30kV.
• Maximum ion beam current: 20nA in 15steps.
• Ion beam resolution: 7.0nm @ 30kV.
• Minimum dwell time: 50ns/pixel.
FIB limitations are essentially in its relative high cost, in a slow device-to-device fabrication and in
the target contamination (in the case of a gallium ion source).
3.3.2 FIB prototyping examples
A FIB machine is a very versatile tool and has
different modes of operation, as suggested in
Figure 3.17.
Ion imaging, at low beam energy.
Ion milling, at high beam energy.
Ion implantation, at high beam energy.
Gas assisted selective ion milling (XeF 2 , H 2 0).
Gas assisted selective material deposition
(TEOS, platinum).
The FIB prototyping of nano-scale devices is a precise way to obtain structures with sub-100nm
dimensions, without masks, resist and etching.
As a first example, the work proposed in 2005 by [Wu05] is a smart use of FIB direct milling for the
fabrication of silicon island arrays. Authors study the effect of beam spot distortion and broadening
on the milled structure.
1. FEI Nova 600 Nanolab DualBeam.
See: http://cmi.epfl.ch/nanotools/FEINova600Nanolab/FEINova600Nanolab_table_of_contents.html

Focused ion beam prototyping 91
Single electron transistor fabrication using FIB direct technique has not been extensively reported
yet. However, a considerable work [Kum06] was published in 2005 by a research group from
Michigan Technological University (MTU).
TJ
Ni island
G
D S
Al 2 O 3
Figure 3.18: FIB micro-milling of a single
electron transistor, proposed by [Kum06], with a
zoom on the 50nm diameter SET island.
At EPFL, we have investigated two techniques of SET fabrication with FIB etching: SOI direct
milling and Resist milling and pattern transfer.
3.3.3 SOI direct milling
TJ
In the MTU device shown in Figure 3.18, FIB
milling is used to cut a thin Ni layer in a 3terminal
mono-island SET configuration with a
lateral gate. About 6 minutes of FIB milling per
device are needed. A 20nm thick Al 2 O 3 layer
was used as tunnel dielectric material and the
conducting island diameter reported is as large
as 50nm.
However, room temperature measurements are
not demonstrating I D -V G CB oscillating
characteristics. Further experiments, as well as
island size reduction, seem mandatory to
improve device performances. Nevertheless, the
use of Ni combined with Al 2 O 3 has the
advantage not to be sensitive to gallium
contamination, compared to Si devices.
The original EPFL process technique presented in this section has been reported in [Pot06b].
Aluminum-gated silicon wires with 8nm diameter and 50-200nm length are demonstrated. The two
configurations (doping levels) are (i) phosphorus highly-doped silicon wires or (ii) un-doped wires
built in a pseudo-MOS configuration.
The Figure 3.19 is a three-dimensional device schematic.
50nm
SOI
Drain
100nm
FIB milling
Aluminum
front gate
Source
Thinned
SOI
SOI
Si substrate
Buried oxide
Figure 3.19: Device sketch of a FIB-prototyped nanowire. The key part of this process is the direct
milling of thin SOI to form the conductive wire. The SEM picture inset is a view of a 100nm long
and 50nm wide cut channel.

92 CHAPTER 3: Hybrid SET/MOS technology
Highly doped silicon wire process flow
The objective of this process is to connect a SOI wire between two SOI electrodes, acting as drain
and source. We used 4’’ SOI wafers with a boron low-doped (10 13 cm -3 ) and 340nm thick SOI layer.
The buried oxide is 400nm. In the central part of the device, the SOI thickness is reduced down to a
30nm thickness by successive oxidation and SiO 2 etch (See “Appendix A: PBL and SOI oxidation”
on page 141.) Then source, drain and a wide channel are defined by basic photolithography and
preliminary SOI etch (see Figure 3.19). The structure is ready for FIB cut, which will reduce the
channel width as small as 30nm. A low 10pA ionic current is used to assure a high resolution.
We performed then HCl decontamination to eliminate surface traces of gallium ions [Sak99]. As
explained in further development, the role of Ga+ ions is critical. The wire is then oxidized in order
to (i) decrease its size from 30nm to a 12nm diameter channel and (ii) to grow a 38nm all around gate
oxide. This oxidation was performed into a dry O 2 atmosphere at T=900°C.
A phosphorus implantation is then applied to the SOI layer through the gate oxide. A doping
concentration in the order of 3x10 20 cm -3 in SOI is achieved in order to make the silicon wire highly
conductive. This implantation is followed by an 880°C annealing step carried out into a slightly
oxidant atmosphere in order to reduce the ionized impurities level in the gate oxide (Figure 3.21).
The final silicon thickness, which corresponds to wire diameter, is decreased from 12nm to 8nm.
This operation has to be well controlled and may result in some wires full oxidation (essentially due
to FIB process variation).
Last process steps correspond to contact opening and metallization. A 800nm thick sputtered AlSi1%
layer is used for drain and source contacts as well as for the gate. This is followed by
photolithography, metal etch and post-metallization anneal (PMA) at T=425°C under a combined N 2
+ H 2 atmosphere. This is mandatory to have ohmic Al/Si contacts.
SOI 8nm
D
Thin
wire
S
SOI
FIB
cut
Al 800nm
BOX 400nm
SOI
BOX
1μm BOX 4μm Handle Si
(a) (b) (c)
Figure 3.20: (a) SEM picture of a 2μm long x 200nm wide FIB cut SOI nanowire. (b) SEM picture
of a gated silicon nanowire with 800nm deposited aluminum. (c) FIB cross-section of the gate stack
corresponding to picture (b).
Total phosphorus concentration [cm -3 ]
10 21
10 20
10 19
38nm
Gate
oxide
Segregation
effect
Figure 3.21: Simulation of the total phosphorus concentration after implantation and oxidizing
annealing. The active doping level in the final SOI active layer is 3x10 20 cm -3 while a segregation
effect in the gate oxide is observed. This helps reducing gate oxide leakage.
Al
8nm
SOI BOX
Dimension [nm]

Focused ion beam prototyping 93
The gallium contamination problem
We highly suspect Ga + ions to have a predominant role in the transport characteristics in Si
nanowires. The use of FIB as a microelectronic-compatible tool is discussed for many years. Almost
all IC industries does not allow FIB processed wafers to return to the production line.
Different tests can be considered to highlight the impact and quantity of gallium dopants in SOI
channels. For example SIMS (Secondary Ion Mass Spectrometry) is used to measure dopant profile
in a layer. This technique is based on ionic etch of the layer and mass spectrometric analysis of
sputtered material. However, SIMS is a costly technique and gives no information on gallium role in
the electronic transport.
We made the following test to emphasize the role of gallium atoms in silicon. First we cut some SOI
samples by FIB milling. After SEM imaging, these structure look perfect (see Figure 3.20a). The
only difference observed is a silicon contrast difference in cut zones and in non-cut zones (cut zones
are brighter, i.e. more conductive). Then we oxidize the structure (gate oxide growth), implant with
phosphorus and anneal the structures, exactly as described in the process flow. By SEM imaging,
structures always look perfect.
Finally, we release the grown oxide in a BHF bath during a short time. We were expecting to see
suspended nanowires cross-connected between two pads, but we had an unforeseeable result, as
displayed in Figure 3.22.
The FIB design used in this test is a double channel connection. An anomalous roughness was only
observed in the surrounding of FIB processed devices.
1μm
Channels
etched
FIB etching
BOX
SEM picture showing
anomalous roughness
SOI
D S
Figure 3.22: SEM picture of a double channel FIB cut (left) and the expected design (center). SOI
channels are completely removed and an uncontrolled silicon roughness appears. A reference non
FIB-cut structure on the same wafer shows a perfectly clean and normal device (right).
This test clearly demonstrates that Ga + ions are changing the silicon structure in a not-controllable
way. It seems that a silicon amorphous layer is created due to Ga + implantation and that gallium
decontamination with HCl is not efficient enough. During oxidation, Ga + ions seem also to
considerably increase the oxide growth rate, resulting in devices over-oxidation. However, there are
surprisingly only few documents in the literature dealing with this problematic.
In order to avoid Ga + contaminations, some authors have pushed a lot of effort in the development of
Si ions source. A nice investigation is reported by Bischoff and al. [Bis04]. The use of Au 82 Si 18
eutectic source for Si ions production is proposed, with a reasonably low melting temperature of
365°C. The surface tension coefficient with temperature of this alloy allow a specific ionic emission.
The Si ions are subsequently mass separated from the beam. Further investigations are however
required in terms of ions spectrometry, ionization and low temperature emission.
A literature review and results comparison are proposed in Table 3.2. The three publications
considered are all discussing the gallium/silicon interaction. All authors estimate that an
amorphization layer is obtained due to FIB machining. At low dose, the gallium is implanted in
silicon, while at higher dose a combined effect of sputtering and implantation appears. It was also
observed by [Leh00] that Ga + contaminants are projected and redeposited up to 400μm from the
beam/wafer impact point! However, these reports are not giving any information on Ga + ions effect
during silicon oxidation.
FIB
Expected
design
I DS
1μm
SOI
BOX
No FIB cut
(reference)

94 CHAPTER 3: Hybrid SET/MOS technology
TABLE 3.2: DEFECT AND GALLIUM CONTAMINATION DUE TO FIB MACHINING.
Reference [Ste92] [Leh00] [Xia06]
Year 1992 2000 2006
Beam source Vertical Ga + beam Vertical Ga + beam Vertical Ga + beam
Dose >10 15 cm -2 (medium) 10 14 cm -2 (low) various
Energy 30keV 30keV 10 to 30keV
Ionic beam current 12pA max: 7nA -
Max. implant ~10 21 cm -3 ~5x10 19 cm -3 -
Max. implant depth
(vertical)
Amorphization depth -
3.3.4 Resist milling and pattern transfer
20 to 30nm ~26nm 10 to 100nm
~50nm
(by TEM analysis)
10 to 100nm and
surface defects
Test structure used p-n junction SIMS analysis Schottky contacts
Remarks
Ga-implanted silicon
is not etched by KOH
Low dose for SIM.
Implant depends on
Si-crystal orientation
Ga + ions produce
acceptors like defects
in silicon
The second experiment we made in order to avoid gallium ions cross-contamination consists in using
an anti-diffusion resist layer, to cut the resist by FIB and to transfer the structures in oxide or in
silicon by reactive ion etching.
Before starting a full process, we made a simple test, as displayed in Figure 3.23. The idea was to
collect all Ga + ions in the resist layer and to transfer the pattern into silicon through a sacrificial
oxide layer. The process flow is the following:
• SOI test wafer
• 200nm deposited SiO 2 as hard mask
• Pattern photolithography and etch: step corresp. to schematic in Figure 3.23 (right)
• 450nm positive resist spin coating 1
• About 450nm depth FIB milling (10pA ionic current): step corresp. to Figure 3.23 (left)
• 200nm anisotropic reactive ion etching (fluorine based plasma)
• Resist removal in O 2 plasma (P=1000W, t=60min.): step corresp. to Figure 3.23 (center)
• Piranha cleaning (H 2 SO 4 96% + H 2 O 2 30%) at T=100°C
1μm Resist
Si
SiO2 SOI
BOX
Resist SiO2 SEM picture:
FIB-cut structures
SEM picture:
resist released
Handle Si
Test structure
Figure 3.23: Resist cut FIB test. The SEM picture on the left shows rectangle apertures directly cut
in the resist. The central SEM picture represents the same test structure after pattern transfer, oxygen
plasma and piranha cleaning. The cross-section on the left depicts the layer stack used for this test.
1. Shipley Microposit S1805
1μm Parasitic SiO2 layer
FIB FIB

Focused ion beam prototyping 95
We observe in Figure 3.23 that a thin parasitic layer is formed after resist removal. This is difficult to
know whether this layer is originated by the resist or by the oxide layer. However, these small sheets
are neither removed by O 2 plasma nor by H 2 SO 4 cleaning bath. Our hypothesis is that Ga + ions are
laterally implanted in the resist/SiO 2 after FIB processing and cannot be released afterwards.
The two approaches used (SOI direct milling and Resist milling and pattern transfer) have many
drawbacks:
• A not-acceptable silicon Ga + contamination
• Fuzzy effect during Ga + contaminated silicon oxidation, generating roughness
• Resist inter-layer cut seems doable but requires more investigation
• Ultra slow device per device processing
• A relatively high cost of process
We took the decision to stop FIB investigations.
3.3.5 Non FIB-cut devices measurement
Measurements presented in this section are non FIB-cut large (2x2μm 2 ) SOI devices. Despite the
large size of the active area, it could be of high interest to probe thin and highly doped devices.
As the Coulomb Blockade is highly dependent from temperature, cryogenic characterization is
needed. We used a closed cycle liquid helium cryostat refrigerator 1 , based on the Gifford-McMahon
thermodynamic cycle. This allows measurement from T=4.2°C up to T=400°C with a very good
precision (ΔT

96 CHAPTER 3: Hybrid SET/MOS technology
The impact of temperature on the I D -V G characteristics presented in Figure 3.25 is showing a net
decrease of current in the ON-regime (accumulation). This is explained by the freezing out of donor
ions. At T=300K, the I ON /I OFF ratio is 5 decades, reduced to 2 decades at T=40K and to a fully wire
blockade at T=8K.
We observe pA-range oscillating characteristics at T

Gate-all-around nanowires on bulk silicon 97
3.4 Gate-all-around nanowires on bulk silicon
Gate-all-around (GAA) silicon nanowires (NW) are considered as an attractive structure for ultrascaled
silicon devices. Many designs have been proposed and fabricated. Furthermore, silicon-based
nanowires operated as single electron transistors seem to be now the most promising structure for
Coulomb blockade (CB) devices and related integrated circuit applications (see Section 2.2 - The
crystalline silicon SET: geometry and architecture). GAA-SET enable also the co-integration with
CMOS devices for low power circuit applications.
We propose in this section an original integration process to fabricate silicon wires on a bulk silicon
wafer, with a polysilicon GAA geometry, providing so an excellent electrostatic control of the
channel. Demonstration of regular SET characteristics in small wires at low temperature and
MOSFET characteristics in large wires are reported, discussed and analyzed in Chapter 4. A 3Dschematic
of a gate-all-around transistor is shown in Figure 3.27.
Figure 3.27: (a) Layout of a GAA-MOSFET with a cut through the channel. (b) SEM cross-section
view of a triangular GAA-MOSFET with dimensions. (c) Schematic 3D view of a GAA-MOSFET.
An LPCVD oxide layer (LTO) is deposited and serves as local buried oxide.
The original technology presented in this section was presented at ESSDERC 2006 [Pot06a] and
recently published in IEEE Transactions on Nanotechnology in 2007 [Mos07a].
Very similar results have been recently published by the National University of Singapore, under the
reference [Sin06]. Authors from Singapore have however access to higher resolution lithography 1 .
3.4.1 Device fabrication and morphology
G
S
D
SiO 2
polySi
(a) (b)
The fabrication presented in this section is a generic process for GAA devices. We have tested
different variants, mainly in terms of layer thickness, gate oxide growth and etching recipes.
The n-type GAA transistors are realized on a low doped (boron 1x10 15 cm -3 ) bulk silicon
wafer. The left-side column of Figure 3.28 shows a lateral source-drain cross-section of the
fabrication steps and the right one presents a channel cross-section view of the same process.
The process starts with the growth of 25nm of oxide and the deposition of 100nm of LPCVD nitride.
Then, source, drain and channel dimensions are defined by optical lithography 2 . Nitride, oxide and
silicon substrate are etched by anisotropic etch in a fluorine-based plasma reactor 3 . Then, 35nm
nitride spacers are LPCVD deposited to protect the lateral side-wall of the wire from the isotropic
etch of the silicon, which is the key step of the proposed processing. The tight control of isotropic
etching in SF 6 plasma (etch rate: 250nm/min) enables the control of the channel dimensions.
1. To have excellent competitors is a demonstration not to be on a totally wrong way! (author’s note)
2. Heidelberg DWL200 direct writing laser. See: http://cmi.epfl.ch/photo/home_photo.html
3. Alcatel 601E system. See: http://cmi.epfl.ch/etch/601E.html
(c)
188nm
Si
n+ Si n+ Si
IDS Source Drain
polysilicon
122nm
LTO
p-Si

98 CHAPTER 3: Hybrid SET/MOS technology
Nitride
p-silicon
SiO 2
Air gap
Source Drain
B
G
A A’
S D
B’
Isotropic
dry etch
Spacers
silicon
Nitride
silicon
Lithographic
dimension:
L>800nm
10μm
200nm
silicon
AA’ cross-section BB’ cross-section
Figure 3.28: The layout of a GAA SiNW transistor is represented on the top. Two AA’ and BB’
cross-sections show the first steps of the integration process. The AA’ SEM picture is a tilted-view of
a 10μm silicon wire after nitride and SiO2 removal. The BB’ SEM picture highlights how the wire is
etched during the isotropic plasma process. In this picture, the wire is still connected to the bulk.
After the isotropic etch, a wet oxide (400nm) is grown to define the final dimension of the silicon
wire and to reduce residual side roughness. The wet oxide and the remaining nitride are removed and
replaced by a low temperature oxide (LTO) before the planarization (CMP) step. The planarization
step is essential to prepare the wire release while keeping a significant oxide thickness on the
substrate. Wire release is performed in a BHF bath.
A 10 to 20nm gate oxide is then grown at T=880 to 950°C, respectively. Oxidation is followed by a
deposition of a 500nm LPCVD polysilicon layer. The polysilicon is patterned and etched in an
isotropic SF 6 plasma. The GAA transistor source, drain and gate are then self-aligned and implanted
with a phosphorous dose of 3x10 15 cm -2 at 50keV, with a standard 7° beam tilt.
Source Wire Drain
silicon
LTO
Phosphorous implantation
Polysilicon
Sour S Drai D
ce
silicon
n
S
D
PolySi
2μm
LTO
silicon
silicon wire
Phosphorous implantation
AA’ cross section BB’ cross section
Figure 3.29: Process showing the gate stack integration. SEM images correspond to the gate level.
AA’ and BB’ cross-section are defined in Figure 3.28.
LTO
silicon
SiO 2
PolySi
Si wire
Polysilicon
500nm

Gate-all-around nanowires on bulk silicon 99
After implant, activation is done at 950°C during 15 minutes under pure N 2 atmosphere. This is not
only essential for S/D overlap regions beneath the gate, but also to ensure a uniformly dopant
diffusion all around the channel. Dopant diffusion reduces also the electrical channel length.
A 500nm LTO passivation layer is deposited and contacts are opened by an anisotropic etch plasma
followed by a BHF bath. Metal pads are done with 800nm sputtered AlSi1% and are partly etched in
a chlorine-based plasma reactor 1 , resulting in vertical sidewalls. The final AlSi etch is done in a wet
ANP bath. ANP 2 is a solution of acetic, nitric and phosphoric acid and is used because of its
selectivity with the underneath LTO layer.
The last step is a post metallization annealing (PMA) of AlSi contacts. This is performed at T=425°C
under a 95% N 2 and 5% H 2 atmosphere. PMA serves both to improve the metal/silicon contact
resistance and to reduce Si/SiO 2 interface dandling bonds by hydrogen passivation 3 . The final
captions of a GAA transistor are depicted in Figure 3.30.
AlSi 1%
p-silicon
G
S LT D
Polysilic LTO
O
n PolySi
on n
n+
n+
+
+
Figure 3.30: Gate-all-around SiNW transistor at the final step of processing.
Cross-sections orientations are defined in Figure 3.28.
The proposed technology offers some clear advantages:
LT
LTO
O
p-silicon
• Substrate is a low-cost bulk wafer, with a perfect doping level control.
• The channel size and shape is controlled by isotropic etch and sacrificial oxidation.
• Source and drain contacts are excellent (purely ohmic).
• Top-down approach, using only fast and low-cost optical lithography.
• The wire is a local-SOI with a GAA geometry for an optimal channel potential control.
• Defect-free Si/SiO 2 interface.
• Excellent yield.
Different SEM pictures taken during the GAA process are proposed in Figure 3.31.
(a)
S
silicon
(b)
S
silicon
2μm
10μm
AA’ cross section BB’ cross section
(c)
Figure 3.31: (a & b) Tilted-views of fully released silicon nanowires with different dimensions.
(c) A fully contacted 5μm long silicon nanowire transistor.
1. STS Multiplex ICP reactor. See: http://cmi.epfl.ch/etch/STS.html
2. CH 3 COOH 100% - HNO 3 70% - H 3 PO 4 85% (ratio 5:3:75)
3. Centrotherm tube. http://cmi.epfl.ch/thinfilms/Tube_1-3.htm
D
D
Al
AlSi 1%
Polysilicon
LTO
Gate
Polysilic
Polysilicon
on
5μm
Si Si
Al

100 CHAPTER 3: Hybrid SET/MOS technology
3.4.2 TEM observation and cross-section shape
Transmission Electron Microscopy 1 (TEM) was done at the EPFL Interdisciplinary Centre for
Electron Microscopy 2 . The first device observed is a transversal cross-section of a 10μm long silicon
nanowire. This sample was cut with a FIB DualBeam 3 , extracted with a transfer tip and thinned
down to a thickness of about 50nm. Sample fabrication details are presented in Figure 3.32.
Platinum
deposition
Lamella
partial
release
Lamella
soldering
with Pt
Transfer
and
soldering to
a metal
support
(a) (b)
Al
5μm
(c) (d)
(e) (f)
(g) (h)
Figure 3.32: SEM pictures representing the main steps of a TEM lamella preparation. Various tilts,
zooms and SEM detectors are used during this preparation.
1. Philips CM 300 FEG
2. See: http://cime.epfl.ch/
3. See Section 3.3.1
Al
Pt
PolySi
FIB cut
Extraction
tip
Lamella
extraction
Lamella
final
thinning by
FIB cut

Gate-all-around nanowires on bulk silicon 101
We observed the cross-section presented in Figure 3.33. This special device had an extra sacrificial
oxidation step during the process. The cross-section obtained is quasi-circular.
(a) (b)
SiNW
PolySi
LTO
SiO2 Figure 3.33: (a) TEM picture of a GAA nanowire MOSFET device, corresponding to Figure 3.32.
(b) High resolution TEM image of the central circular nanowire with atomic resolution. The SiNW
diameter is 5nm and gate oxide thickness is 10nm.
The 5nm sample in Figure 3.33 is the smallest cross-section size we have obtained with this process.
This size seems the limit we can achieve with this technology. Indeed, very small and long wires are
very fragile structures and can break during processing. Furthermore, smaller wires are bent,
probably due to stress accumulated during the process (See Raman measurements on page 118). An
example of a small released wire is shown in Figure 3.31 (a). Details will be presented at IEDM 2007
[Mos07b].
Depending on design channel width, isotropic silicon etch and sacrificial oxidation, we also have
experimentally obtained large cross-sections with various shapes and dimensions. Three different
FIB cross-sections are shown in Figure 3.34.
PolySi
120nm
Si
1μm 5nm
PolySi
540nm
LTO LTO
LTO
Si
(a) (b) (c)
SiO 2
PolySi
480nm
SiNW
PolySi
Figure 3.34: SEM pictures of FIB cut samples. The device (a) is a triangular gate-all-around SiNW,
the device (b) is a Ω-gate transistor and the device (c) is a pentagonal transistor.
In the reported samples, the effective width denotes the perimeter of the cross section measured on a
FIB cut of the device. The planar dimension is simply the dimension measured on top of the layout.
We have measured devices having lengths ranging from 1 to 10μm (see Chapter 4). Furthermore,
during the fabrication, the wire length gets slightly longer than its nominal layout dimension due to
the combined effect of silicon isotropic etch and sacrificial oxidation at S/D sides.
As can be seen in Figure 3.31, the width of the channel is not constant, but widens out at the source
and drain sides. In order to evaluate how much of the total drain bias is dropped over the center
region of the device, we can divide the device into three sections of differing width and length, two
sections represent the ends of the device W S/D /L S/D , whereas a single section W wire /L wire
characterizes the center region. Details are discussed in [Mos07a]. We estimate that the width
variations are on the order of 10% for a L=10μm device.
Si

102 CHAPTER 3: Hybrid SET/MOS technology
3.4.3 The implant and anneal matter
The proposed process is auto-aligned. This means that the polysilicon gate and the silicon source and
drain areas are doped during the same implant and annealing steps. There are many auto-aligned
options for the gate integration. A summary of main variants we considered during this work are in
the flow chart, Figure 3.35.
Un-doped LPCVD
polysilicon deposition
In-situ doped LPCVD
polysilicon deposition
Metal gate
deposition (Mo, W)
Silicidation
Poly etch
Poly implant
POCl 3 poly
doping
Poly implant
Metal etch S/D implant S/D anneal
Figure 3.35: Flow chart representing main gate and S/D integration variants. The one we choose is
displayed in the second line (in italics). This is the cheapest and fastest option regarding to the CMI-
EPFL available facilities.
We encounter in our gate integration a drawback that needs a lot of care. The same implant is used
for both gate doping and for silicon S/D contacts. However, dopants diffusion should be quite large
in the polysilicon gate in order to give a constant doping level all-around the silicon wire. At the
contrary, dopants diffusion should be limited at S/D sides, to control junctions depth and to avoid S/D
junctions punch-through.
The doping trade-off has been studied and calibrated by 2D TCAD process simulation 1 . The example
we propose in Figure 3.36 is a pentagonal gate MOSFET device.
In this example, a gate stack consisting of 10nm thermal oxide and 100nm polysilicon is created. The
polysilicon gate is patterned and isotropically etched, and a self-aligned implantation step of gate,
source and drain is carried out (Arsenic, 5x10 15 cm -2 , 40keV, Tilt=7°) using a 40nm thick
implantation oxide, which is subsequently removed. Arsenic is used instead of phosphorous because
of its lower diffusivity in silicon. The doping is activated at 950°C during 10min.
Because of the 3D geometry of the device along with the low diffusivity of arsenic, a part of the gate
on the lower concave part of the sidewalls is low-doped, which may leads in an insufficient channel
potential control. However, foreseen solutions are in the flow chart, in Figure 3.35.
Low-doped
region
SiO 2
p-silicon
PolySi
480nm
90nm
Poly etch S/D implant
Poly oxidation
Figure 3.36: (Left) 2D finite element simulation, with doping level in polysilicon. (Left) FIB crosssection
of a fabricated pentagonal gate device on which we modelled the simulation.
1. DIOS Synopsys TCAD. See: http://www.synopsys.com/products/tcad/tcad.html
S/D anneal
Gate + S/D
implant
Poly etch Poly oxidation S/D implant S/D anneal
Poly etch Poly oxidation S/D implant S/D anneal
Poly etch Poly oxidation S/D implant S/D anneal
Doping
concentration [cm -3 ]
480nm
Gate + S/D
anneal
320nm

Gate-all-around SOI devices 103
3.5 Gate-all-around SOI devices
This section presents the last investigated technology for the fabrication of gate-all-around silicon
nanowires. Contrary to the local-SOI process described in the Section 3.4, devices are integrated on
SOI wafers. Short channel lengths with small wire cross-section are targeted. Furthermore, as
explained in the Section 1.4, the SOI platform is also addressing problems like SCE and DIBL.
However, the fabrication platform is still limited to EPFL-CMI facilities, and particularly to a coarse
0.8μm lithographic resolution. The integration would be much better controlled and denser if a stateof-the-art
industrial lithography (resolution 0.1μm or less) would have been used. The Table 3.3
summarizes advantages and limitations of both bulk (local-SOI) and SOI devices.
-
-
-
-
-
+
-
-
3.5.1 SOI wire formation
TABLE 3.3: SOI VS. BULK TECHNOLOGY.
SOI Bulk (local-SOI)
High cost of wafers
SOI/BOX interface quality
Some process difficulties (limited etching
and oxidation, BOX conservation)
Contacts pads (thin SOI)
Rectangular cross-section shape of the
channel only
Perfect S/D isolation
Process variability (dimensions)
Sensitive to self-heating
The SOI nanowires presented in this technology are fabricated using a top-down approach. The SOI
layer is 100nm thick and p-type doped (boron, 10 15 cm -3 ). The buried oxide (BOX) is 400nm thick
and the handle wafer is lightly p-type doped. Wire shapping is described in Figure 3.37.
Figure 3.37: A schematic of the SOI wire formation (channel cross-section). The pictures are
generated by TCAD process simulation.
+
+
+
+
+
-
+
+
Low cost of wafers
No interfaces
Process much less sensitive to technology
variations
Contacts pads (on the substrate)
Many types of cross-section shapes and
dimensions (triangular, Ω-gate,...)
Current leakage to the substrate
Better control of process variations
No self-heating
(a) 800nm (b) Oxidation: 40nm growth
SOI:
100nm
BOX: 400nm
LTO:
400nm
(c) (d) Si isotropic dry etching
(e)
Bulk-Si
SiO2
release
Oxidation: 70nm growth
(f)
Photoresist
SOI wire
SiO2 release

104 CHAPTER 3: Hybrid SET/MOS technology
At the beginning of the process, a 400nm low temperature oxide (LTO) is deposited and the first
lithographic step is implemented. Then, anisotropic etch is used to define the initial SOI section, as
shown in Figure 3.37(a).
After resist removal, a dry oxidation of 40nm growth (T=1000°C under O 2 atmosphere) is applied to
reduce sidewall roughness. Then the oxide sides are released in a BHF bath and SOI is underattacked
in a SF 6 plasma reactor (see Figure 3.37, step d). This etching is highly critical, this
determines the wire cross-section. Unfortunately, at sub-micron scale, the control of dimensions all
over the surface of the wafer is very poor and the generated roughness high.
A second dry oxidation must be applied to reduce the roughness induced by the silicon plasma etch.
In this step, a 70nm thick SiO 2 layer is grown at T=1050°C. The final step of the wire formation
process consists first to lithography define apertures in the central part of the device, and then to
release the LTO and the sacrificial oxide in a BHF bath.
The proposed wire formation deserves the following comments:
• Many process variations can be considered (various steps of under-etching and
sacrificial oxidations).
• The buried oxide is 400nm thick only. During the complete process, a lot of care was
taken in order to preserve it below the wire, because a BOX refill with deposited oxide
is difficult, due to the non-conformal LTO deposition.
It was not possible to keep the BOX in this process, due to successive BHF attacks. The
BOX refilling technique is described in the next steps.
• As a complete BOX removal was observed, it would be better in future SOI wire
fabrication to use - for the SOI wire formation - either sacrificial oxidation than silicon
under-etching (like in local-SOI wires, where wires roughness is almost negligible).
• The height of the SOI wire is partly reduced during the fabrication.
• S/D contacts have to be taken on a not too thin SOI region (T SOI >70nm, see [Oh94]).
As the initial SOI thickness is 100nm, then we did not locally thinned down SOI in the
channel region. The use of a thicker SOI layer may be considered if a correct local SOI
thinning down is integrated in the process flow.
Various SEM pictures of the SOI process are proposed in Figure 3.38.
(a)
BOX
(b) Bulk
(c)
Drain
pad
Source
pad
Platinum
SOI/SiO2 core
Gate-all-around polySi
2μm 1μm 300nm
SOI wire
SOI wire
Bulk
Figure 3.38: (a) A released SOI nanowire connected between two pads, after the wire formation. (b)
A zoom on the same wire. the BOX is completely released but the remaining wire roughness is rather
high and dirt appears at the bulk surface. (c) A FIB cross section of a released 350x30nm SOI wire.
As observed in Figure 3.38 (c), the bulk refilling with LTO did not succeed. Indeed, we observed
voids below the wire, and the release of the wire for the gate stack formation results in a complete
release of the deposited oxide surrounding the wire. We decided to continue the process in spite of
this difficulty. This lack of BOX will result in a large capacitance (surface: 3x6μm 2 ) between the gate
and the bulk, with T ox as a dielectric layer. Gated devices are proposed in Figure 3.41.
A systematic control of dimensions is needed after wire processing and releasing. The wire crosssections
obtained by this process are either rectangular. Dimensions are measured by SEM imaging,
see Figure 3.39. This corresponds to the minimum planar width observed in the central part of the
wire, where the cross-section is minimum.

Gate-all-around SOI devices 105
Figure 3.39: SOI effective width measured by SEM imaging, as a function of the layout width. The
linear trend is about W effective =W layout -0.9μm. This means that about 450nm of SOI is laterally
released on each side of the wire.
3.5.2 Gate stack formation
Next steps in the process, which are common for all device cross-section shapes and dimensions, are
the gate stack integration (see Figure 3.40).
First, the SiO 2 hard mask, as well as any remaining BOX, corresponding to Figure 3.37f, is released
in a BHF mask. Then, a 2-4μm LTO is deposited, and a CMP step is carried out to planarize the
surface. LTO is used as insulating layer between the substrate and the wire.
A BHF etch is then carried out in order to release the silicon wire, while maintaining sufficient
isolation beneath the wire to avoid having a parasitic substrate device. It was observed by SEM
imaging that the void below the wire is not completely refilled. Whatever happens with the LTO, the
gate oxide growth will definitely cancel any risk of short-circuit between the polysilicon gate and the
substrate.
SOI
wire
Handle silicon
Wire release
in a BHF bath
LTO
Void
LPCVD LTO
+
Planarization
Wire partial
release
PolySi
Gate oxide
+
polysilicon
Figure 3.40: Example of passivation and gate integration for a SOI device, emphasizing how a void
is created below the wire and results in a capacitive coupling between the gate and the bulk.
For the gate stack, a conservative 10nm thick SiO 2 is grown as gate dielectric, followed by a LPCVD
polysilicon deposition with a thickness of 300nm. A thin polysilicon layer offers the advantages of a
limited lateral polysilicon extension (essential in scaled-down devices) and a better gate doping
control and uniformity. Contrary to LTO deposition, polysilicon deposition is perfectly conformal.
The gate is patterned and etched in an isotropic SF 6 plasma, which is selective to oxide, so that the
gate oxide acts as an etch-stop layer for the silicon wire. This helps also to reduce the effective
channel etch by under-etching. An oxide of 20nm is then grown to protect the surface during
implantation.
SiO2

106 CHAPTER 3: Hybrid SET/MOS technology
Source, drain and gate are then doped by a self-aligned arsenic implantation step (Dose=2x10 15 cm -2 ,
Energy=35keV, no tilt, simulated junction depth in silicon x j =112nm). Then, a rapid thermal
annealing (RTA) activation step is carried out at 950°C during 45s under Ar atmosphere 1 .
The combination of arsenic and RTA annealing is used to limit as much as possible dopants
diffusion, and to avoid S/D junction short-circuit. However, as explained in the Section 3.4.3, the
auto-aligned process should also dope the polysilicon gate. This will inevitably result in partly undoped
gate. SEM pictures of gated devices (W/L=1.5μm/2μm) are proposed in Figure 3.41. The
effect of polysilicon under-etching is significant for the device (c).
After the annealing, a 500nm thick isolation oxide (LTO) is deposited, contact holes are opened by a
combination of dry and wet etching and an 800nm thick AlSi1% is sputtered. The metallization level
is patterned and etched in an ANP bath (CH 3 COOH 100%: HNO 3 70%: H 3 PO 4 85% [5:3:75]). Wet
etching is preferable due to the 3D geometry. In the end, an annealing step at 425°C in an N 2 /H 2
atmosphere is carried out in order to obtain high quality ohmic contacts.
Electrical DC measurements of SOI transistors are proposed in Section 4.4 on page 131.
(a) (b)
BOX
Drain Source
2μm PolySi
1μm
Poly
Drain Source
Si
Figure 3.41: SEM pictures of a gated SOI transistor (a) with zoom on the channel (b). A short
channel device obtained by polysilicon under-etching (c).
3.5.3 Rapid thermal annealing qualification
Many tests structures have been included in the design. This is beyond the scope of this thesis to
describe all tests (lithography resolution and alignment, etching, etc.).
However, it was necessary to probe the activation of SOI and polysilicon layers after RTA. For this
purpose, simple resistors have been added in the design. A ohmic I-V linear characteristics has been
measured, proving a correct dopant activation. RTA of arsenic-doped layers is highly difficult to be
correctly simulated, because of the non-uniform thermal profile during the RTA [Van95].
Figure 3.42: Test resistors measurement on SOI and polysilicon layers, after implant and RTA.
1. RTA performed at CNRS-ULP Laboratory, Strasbourg, France.
(c)
1μm
Poly-Si
Drain Source

Process scalability 107
3.6 Process scalability
In this section, the scalability of the two GAA technologies (local-SOI in Section 3.5 & SOI in
Section 3.6) is evaluated.
Scalability of the wire cross-section
Scalability of the wire cross-section, corresponding to a perimeter W eff, was shown to be very good
with dimensions down to W eff=16nm for a local-SOI circular cross-section (Figure 3.33).
Furthermore, shapes and dimensions are linked (large size: pentagonal, medium size: triangular,
small size: circular). A dispersion of dimensions at wafer level due to variations in isotropic silicon
etching exists. Structures in the central part of the 4’’ wafer are etched faster compared with
structures on the sides. The mean silicon etch rate of 250nm/min is very high and should be reduced
for a tight control of dimensions. At the contrary, the use of silicon dry and wet oxidation is a very
accurate technique.
Scalability of the wire length and channel length
Scalability of the silicon wire length is basically limited by the lithographic resolution, for both
local-SOI and SOI wires. As the best resolution is 0.8μm in this work, then the minimal wire length
is limited to slightly above this value due to the 3D geometry. Sacrificial oxidation and isotropic
etching used to form the wire cross-section will also lengthen the silicon wire.
Scalability of the channel length depends on the possibility to pattern and to etch a gate-all-around
polysilicon structure. Channel length depends on the lithographic resolution, but also on the etching
process used to pattern the gate. An increased under-etching, as used in Figure 3.41(c) is difficult to
be controlled but may decrease the channel length by a few hundreds of nanometers. In such a case,
the polysilicon over the wire is shorter than the polysilicon below it, and so the device may behave as
a double gate transistor, the above one with a short L, and the below one with a long L.
Scalability of the gate oxide
It is also highly desirable to reduce the gate oxide thickness in order to increase current drive and
operating frequency. In this technology, a grown 10 to 20nm thick thermal oxide is used as gate
dielectric, which works well with respect to gate leakage and interface defects.
Poly-Si
5nm
SiO2
Si
100nm
Figure 3.43: High resolution TEM image of a
local-SOI triangular GAA MOSFET. The inset
shows an atomic resolution zoom of a corner,
indicating a very sharp silicon angle.
However, there are two potential critical points
in the current process with respect to scalability.
First, oxidation rate is dependent on crystalline
orientation. Thin gate oxides can be difficult to
be controlled in a GAA device. Second, as
explained in [Mos06], corner effects in
triangular geometries (Figure 3.43) can be
exploited to boost the current.
Sharp silicon structures with thin grown gate
oxides can be problematic due to the thinning of
oxide growth in the corners, which is a point
with high electric field induced when the
transistor is turned ON.
Further device optimization will consist in
reducing corner effects and using high-k
dielectrics.

108 CHAPTER 3: Hybrid SET/MOS technology
3.7 Summary
3.7.1 Synopsis
We proposed the following in this chapter:
• The introduction of this chapter is on the need for advanced lithographic systems. Nanoscale
dimensions can be reached by a combination of lithography and smart engineering.
We show how this work was driven by the need of high resolution lithography, and what
was made in order to overcome limitations.
• Lateral pattern definition (Section 3.2)
This process is based on the use of sidewall engineering to transfer a layer thickness in to
a lateral dimension. Three techniques have been investigated (polysilicon oxidation,
silicon oxidation and nitride deposition). Best results have been observed with silicon
oxidation, showing a 70nm minimal dimension and a reduced sides roughness.
Furthermore, the isolation of a single silicon nanowire embedded inside an oxide grown
layer has also been demonstrated and supported by TCAD simulation. However, the
transfer from a single wire to a true operational device was not immediately satisfactory
and it was decided not to go on with this technique.
• Focused Ion Beam prototyping (Section 3.3)
This section briefly reports FIB prototyping for the fast fabrication of SOI nanowires.
FIB is an efficient processing system, but silicon contamination with Ga + ions remains
an unresolved problem. We tested one iteration loop and show some key results.
• Gate-all-around local-SOI devices (Section 3.4)
This original wire integration deserves the gold medal of achievement, compared with
the three other processes considered. We have fabricated silicon wires on bulk silicon,
with a polysilicon GAA geometry, providing so an excellent electrostatic control of the
channel.
We have observed Coulomb Blockade at low temperature and excellent MOSFET
characteristics at room temperature. This process has many advantages, such a very low
cost of integration, excellent S/D contacts and channel crystallinity, and many types of
cross-sections shapes and dimensions, including a minimum 5nm circular diameter. The
gate stack integration is also discussed, and solutions are particularly proposed to
enhance the gate and S/D doping step.
• Gate-all-around SOI wires (Section 3.5)
The last process considered is a transfer of the local-SOI technique to SOI wafers. This
process is motivated by the S/D junction leakage, that limits the operating mode of local-
SOI transistors, and also by the integration of shorter channels. Wire cross-sections are
rectangular, because the sacrificial oxidation - used for the wire formation - has been
strongly reduced. This process results in two major issues, which are first a BOX void
below the wire and second a high sides roughness generated by the isotropic silicon
etching.
In terms of processing, the SOI process should be re-considered. The S/D contacting,
made on a thin SOI layer, is also an issue that does not affect local-SOI devices.
• Local-SOI vs. SOI scalability (Section 3.6)
Scalability discussion is essential. We compared the two most successful processes
studied (local-SOI and SOI) and we conclude that there is no major scalability
differences between these two technologies.
The scalability of the channel cross-section has been shown to be excellent. On the other
hand, the scalability of the wire length and the gate length is dependent on the
lithographic resolution. This should be strongly improved, in order to fulfill ITRS
requirements.

Bibliography 109
3.8 Bibliography
[Ani03] K. G. Anil, K. Henson, S. Biesemans and N. Collaert, ’’Layout density analysis of FinFETs’’,
Proceedings of ESSDERC, pp. 139-142, Estoril PT, 2003.
[Bis04] L. Bischoff, G. L. R. Mair, C. J. Aidinis, C. A. Londos, C. Akhmadaliev and T. Ganetsos, ’’A
Au82Si18 liquid metal field-ion emitter for the production of Si ions: fundamental properties and
mechanisms’’, Ultramicroscopy, vol. 100 (1-2), pp. 1-7, 2004.
[Cho02] Y.-K. Choi, T.-J. King and C. Hu, ’’A spacer patterning technology for nanoscale CMOS’’, IEEE
Transactions on Electron Devices, vol. 49 (3), pp. 436-441, 2002.
[Cho03] Y.-K. Choi, J. Zhu, J. Grunes, J. Bokor, and G. A. Somorjai, ’’Fabrication of sub-10-nm silicon
nanowire arrays by size reduction lithography’’, Journal of Physical Chemistry B, vol. 107, pp.
3340-3343, 2003.
[Deg07] B. Degroote, R. Rooyackers, T. Vandeweyer, N. Collaert, W. Boullart, E. Kunnen, D. Shamiryan, J.
Wouters, J. Van Puymbroeck, A. Dixit and M. Jurczak, ’’Spacer defined FinFET: Active area
patterning of sub-20 nm fins with high density’’, Microelectronic Engineering, vol. 84, pp. 609-618,
2007.
[Fei07] http://www.fei.com/Portals/_default/PDFs/content/2006_06_Nova600NanoLab_pb.pdf (2007).
[Gar01] K. Garikipati and V. S. Rao, ’’Recent advances in models for thermal oxidation of silicon’’, Journal
of Computational Physics, vol. 174 (1), pp. 138-170, 2001.
[Gra04] P. B. Grabiec, M. Zaborowski, K. Domanski, T. Gotszalk and I. W. Rangelow, ’’Nano-width lines
using lateral pattern definition technique for nanoimprint template fabrication’’, Microelectronic
Engineering, vol. 73-74, pp. 599-603, 2004.
[Ito00] T. Ito and S. Okazaki, ’’Pushing the limits of lithography’’, Nature, vol. 406, pp. 1027-1031, 2000.
[Jae02] R. C. Jaeger, ’’Introduction to microelectronic fabrication: Thermal oxidation of silicon’’, Upper
Saddle River: Prentice Hall, New Jersey NJ, 2002.
[Ked97] J. Kedzierski, J. Bokor and C. Kisielowski, ’’Fabrication of planar silicon nanowires on silicon-oninsulator
using stress limited oxidation’’, Journal of Vacuum Science and Technology B, vol. 15 (6),
pp. 2825-2828, 1997.
[Kum06] P. S. Kumar Karre, P. L. Bergstrom, M. Govind and S. P. Karna, ’’Single electron transistor
fabrication using Focused Ion Beam direct write technique’’, Advanced Semiconductor
Manufacturing Conference, pp. 257-260, Boston MA, 2006.
[Leh00] C. Lehrer, L. Frey, S. Petersen, M. Mizutani, M. Takai and H. Ryssel, ’’Defects and galliumcontamination
during focused ion beam micro machining’’, Conference on Ion Implantation
Technology, pp. 695-698, Alpbach AT, 2000.
[Lin05] B. J. Lin, ’’Lithography for manufacturing of sub-65nm nodes and beyond’’, Technical Digest of
IEDM, pp. 48-51, Washington DC, 2005.
[Lit06] The International Roadmap for Semiconductor, ’’Lithography’’, 2006 Edition, available online at
http://www.itrs.net/, 2006.
[Mel03] N. A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P. M. Petroff and J. R. Heath,
’’Ultrahigh-density nanowire lattices and circuits’’, Science, vol. 300, pp. 112-115, 2003.
[Mos06] K. E. Moselund, D. Bouvet, L. Tschuor, V. Pott, P. Dainesi and A. M. Ionescu, ’’Local volume
inversion and corner effects in triangular gate-all-around MOSFETs’’, Proceedings of ESSDERC,
pp. 359-362, Montreux CH, 2006.
[Mos07a] K. E. Moselund, D. Bouvet, L. Tschuor, V. Pott, P. Dainesi, C. Eggimann, N. Le Thomas, R. Houdré
and A. M. Ionescu, ’’Co-integration of gate-all-around MOSFETs and local silicon-on-insulator
optical waveguides on bulk silicon’’, IEEE Transactions on Nanotechnology, vol. 6 (1), pp. 118-125,
2007.
[Mos07b] K. E. Moselund, P. Dobrosz, S. Olsen, V. Pott, A. O’Neill, L. De Michielis, D. Tsamados, D. Bouvet,
A. O’Neill and A. M. Ionescu, ’’Bended gate-all-around nanowire MOSFET: a device with
enhanced carrier mobility due to oxidation-induced tensile stress’’, Technical Digest of IEDM,
Washington DC, 2007.
[Oh94] C.-B. Oh, J. Ahn, S. Lee, Y.-W. Kim, D. Kim and B. Kim, ’’Series resistance at metal contact for
thin film SOI MOSFET’’, Proceedings of the SOI Conference, pp. 43-44, Nantucket Island MA,
1994.

110 CHAPTER 3: Hybrid SET/MOS technology
[Orl03] J. Orloff, M. Utlaut and L. Swanson, ’’High resolution Focused Ion Beams: FIB and its application’’,
Kluwer Academic Publishers, New-York NY, 2003.
[Pot05] V. Pott, D. Grogg, J. Brugger and A. M. Ionescu, ’’Silicon nanowires patterning by sidewall and
nano-oxidation processing’’, Proceedings of Nanoelectronics Days, pp. 19-20, FZ Jülich DE, 2005.
[Pot06a] V. Pott, D. Bouvet, J. Boucart, L. Tschuor, K. E. Moselund and A. M. Ionescu, ’’Low temperature
single electron characteristics in gate-all-around MOSFETs’’, Proceedings of ESSDERC, pp. 427-
430, Montreux CH, 2006.
[Pot06b] V. Pott and A. M. Ionescu, ’’Conduction in ultra-thin SOI nanowires prototyped by FIB milling’’,
Microelectronic Engineering, vol. 83 (4-9), pp. 1718-1720, 2006.
[Sak99] T. Sakata, T. Ogiwara, H. Takahashi and T. Sekine, ’’Investigation of Ga contamination due to
analysis by dual beam FIB’’, Proceedings of ATS, pp. 389-393, Shanghai CN, 1999.
[Sin06] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, C. H. Tung, K. M. Hoe, S.
R. Omampuliyur, D. Tripathi, A. O. Adeyeye, G. Q. Lo, N. Balasubramanian and D. L. Kwong,
’’Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channelorientation
and low temperature on device performance’’, Technical Digest of IEDM, pp. 1-4, San
Francisco CA, 2006.
[Ste92] A. J. Steckl, H. C. Mogul and S. Mogren, ’’Localized fabrication of Si nanostructures by focused ion
beam implantation’’, Applied Physics Letters, vol. 60 (15), pp. 1833-1835, 1992.
[Uch02] K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata and S. Takagi, ’’Experimental study on
carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5
nm’’, Technical Digest of IEDM, pp. 47-50, San Francisco CA, 2002.
[Van95] E. Vandenbossche, H. Jaouen and B. Baccus, ’’Modeling arsenic activation and diffusion during
furnace and rapid thermal annealing’’, Technical Digest of IEDM, pp. 81-84, Washington DC, 1995.
[Wu05] S.-E. Wu and C.-P. Liu, ’’Direct writing of Si island arrays by focused ion beam milling’’,
Nanotechnology, vol. 16 (11), pp. 2507-2511, 2005.
[Xia06] L. Xia, W. Wu, Y. Wang and J. Xu, ’’Characterization of focused-ion-beam damage in n-type silicon
using Schottky contact’’, Applied Physics Letters, vol. 88 (15), 152108, 2006.
[Zab06] M. Zaborowski, D. Szmigiel, T. Gotszalk, K. Ivanova, Y. Sarov, T. Ivanov, B. E. Volland, I. W.
Rangelow and P. Grabiec, ’’Nano-line width control and standards using Lateral Pattern Definition
technique’’, Microelectronic Engineering, vol. 83, pp. 1555-1558, 2006.

Chapter 4
Characterization and analysis
This chapter presents electrical measurements of local-SOI and SOI transistors. Analysis and
discussion of obtained results are proposed.
The chapter starts with an introduction on probing facilities and measurement setup. An equivalent
electrical schematic of a local-SOI transistor is also shown. Then, local-SOI device measurements
are reported from low temperature up to 150°C and excellent characteristics in terms of electron low
field mobility, threshold voltage control and subthreshold slope are demonstrated. Electron mobility
extraction shows values up to 850cm 2 /Vs at room temperature, in devices with triangular crosssections.
Complementary micro-Raman spectroscopy suggests a process-induced strain distribution along
suspended wires that is responsible for mobility enhancement.
On the shortest devices, cryogenic (T

112 CHAPTER 4: Characterization and analysis
4.1 The probe setup
During this thesis, many wafers and devices have been fabricated. An optimal probing strategy,
depending on available EPFL facilities, is essential. This was performed directly on full wafers,
excepted for FIB prototyped devices (see Section 3.3). A full wafer characterization is much faster
and simpler than sample probing, where chip dicing, packaging and bonding are necessary.
The temperature on the surface of the wafer needs to be perfectly controlled. In order to have a good
thermal and electrical contact between the chuck and the wafers, the backside of all tested wafers
(bulk and SOI) have been cleaned by CMP polishing. This removes easily deposited layers and any
dust that may isolate the backside from the metallic chuck. Furthermore, an indium foil is always put
between the wafer and the chuck to increase thermal and electrical conductivity. All electrical
characterization have been carried out using Agilent Technologies HP analyzers of the 415X family 1 .
The Figure 4.1 shows the typical 4-probe arrangement used for the measurement presented in this
chapter. The complete setup 2 is inside a vacuum chamber, under dark, where the temperature can be
precisely controlled from T=4.2K up to T=450K.
Figure 4.1: Picture of the measurement setup used for the complete characterization of devices. The
moving stage with the wafer is fixed below a metallic shield. Four DC tungsten tips are used to probe
devices. Two additional RF probes are also visible but not used in this work.
The gate-all-around transistor on bulk silicon
The Figure 4.2 depicts an equivalent electrical schematic of a GAA MOSFET device. During
measurement, bulk and source contacts are grounded. V D is a positive voltage in order to reverse
biased the drain/bulk diode. The silicon nanowire threshold voltage is insensitive to any reverse
substrate bias, due to the strong electrostatic shielding operated by the GAA-structure.
V D
n+
p
silicon
V G
I ID V S
150nm oxideLTO
n+
p
V VBULK BULK
Figure 4.2: Gate-all-around MOSFET electrical schematic.
1. See: http://www.agilent.com
2. Süss MicroTec PMC150 - Manual cryogenic probe station.
See: http://www.suss.com/products/test_systems/dedicated_systems/cryogenic_probe_systems

Gate-all-around MOS characterization 113
4.2 Gate-all-around MOS characterization
4.2.1 Room temperature characteristics
This section presents characteristics measured on bulk GAA transistors. Figures 4.3 to 4.8 show
static I D-V G and I D-V D electrical characteristics of three 10μm long transistors with different crosssection
shapes and dimensions. The effective width W eff and gate oxide thickness t ox are indicated on
the graphics. Devices SEM/TEM pictures are inset in Figure 4.12.
In terms of performances, all devices have a very low I OFF current of about 0.1pA to 0.5pA, which is
a signature of low-defect Si/SiO 2 interface. Similarly, both gate leakage current and bulk leakage
current measured are negligible.
Figure 4.3: Room temperature I D -V G characteristics (linear and logarithmic scales) of a Ω-gate
device. The channel length is 10μm and the gate oxide thickness is 20nm.
Figure 4.4: Room temperature I D -V D characteristics of a Ω-gate device. The channel length is 10μm
and the gate oxide thickness is 20nm.

114 CHAPTER 4: Characterization and analysis
Figure 4.5: Room temperature I D -V G characteristics (linear and logarithmic scales) of a GAA
triangular device. The channel length is 10μm and the gate oxide thickness is 20nm.
Figure 4.6: Room temperature I D -V D characteristics of a GAA triangular device. The channel length
is 10μm and the gate oxide thickness is 20nm.
Figure 4.7: Room temperature I D -V G characteristics (linear and logarithmic scales) of a GAA
circular device. The channel length is 10μm and the gate oxide thickness is 10nm.

Gate-all-around MOS characterization 115
Figure 4.8: Room temperature I D-V D characteristics of a GAA circular device. The channel length is
10μm and the gate oxide thickness is 10nm.
When reducing the cross-section of the devices, a large increase in both I ON current and wire current
density is observed, as shown in Table 4.1. The current level in the small circular wire, with a 10nm
gate oxide, is remarkably high [Pot06a]. Shorter devices (minimum channel length L=1μm) have a
much higher current level, see Figure 4.16.
TABLE 4.1: ON-CURRENT CHARACTERISTICS OF THREE DEVICE STRUCTURES.
Device Ω-gate Triangular Circular
L 10μm 10μm 10μm
Weff 1.3μm 300nm 16nm
Gate oxide tox 20nm 20nm 10nm
VG-VT 2V 2V 2V
VD 1V 1V 1V
ION [A] 15.9μA 10.2μA 1.05μA
ION [nA/nm] 12.2nA/nm 34nA/nm 65.6nA/nm
I ON [nA/nm 2 ] N/A a
a. The Ω-gate is not a gate-all-around geometry.
0.79nA/nm 2 13.3nA/nm 2
I D -V D characteristics show that wire contacts are purely ohmic because they are taken on the
enlarged bulk-Si region (see Figure 3.31). This is an advantage in comparison with growth silicon
wires where contacts can be a critical issue. On the 5nm-diameter I D -V D (Figure 4.8), we observe
non significant self-heating effect (negative g DS conductance observed at V G =2V and V D =3V).
Larger and shorter GAA and Ω-gate structures are not sensitive to self-heating due to an excellent
heat transfer into the bulk at S/D contacts.
For a more relevant comparison between the different cross-sections, a normalization factor is
introduced. This is defined by:
tox ⁄ Weff r + tox ln⎛--------------
⎞
⎝ r ⎠
-------------------------
2π
Normalization factor for Ω-gate and triangular devices: (4.1)
Normalization factor for a circular cross-section: (4.2)

116 CHAPTER 4: Characterization and analysis
The normalization factor for a circular cross-sections takes into account the cylindrical geometry
[Coa07], where r=2.5nm and represents the diameter of the silicon core (see Figure 3.33). The
highest transconductance is observed in the triangular cross-section, suggesting enhanced carrier
mobility.
Figure 4.9: Room temperature normalized transconductance characteristics (left axis). On the right
axis, the corresponding drain currents are plotted. Device cross-section sizes correspond to Figures
4.3 to 4.8. Normalization factors are given by Equations 4.1 and 4.2.
4.2.2 Temperature dependent characteristics
Temperature dependent static measurements have been performed on L=10μm long circular,
triangular and Ω-gate devices. All devices are fully functional up to T=150°C. The subthreshold
slope S=dV G /d(log(I D )) of the three different geometries is depicted in Figure 4.10. The slope is
measured in the linear regime at V D =20mV. The three devices have a similarly very small slope
S=70mV/decade at room temperature. However, the subthreshold slope of the 5nm cross section
circular SiNW degrades much faster with the temperature than the two other devices with larger
cross sections.
Figure 4.10: Experimental dependence of the subthreshold slope S on temperature, for three devices.
A good linearity is observed for all devices up to room temperature. The fundamental subthreshold
slope minimum limit is also represented.

Gate-all-around MOS characterization 117
Figure 4.11 (right) shows the threshold voltage (V T ) dependence on temperature. The threshold
voltage is extracted at V D =20mV, using the Ghibaudo method described in [Ghi88], and further
extended in [Ghi97]. This method exploits the linear dependence I D /g m 1/2 vs. VG in the strong
inversion regime (see Equation 4.8 on page 131). It was observed that 5nm-diameter SiNW have
larger V T drift with the temperature in the 200K to 425K range (-2.1mV/K), in comparison with Ωgate
or triangular devices (-0.85mV/K). For the two larger devices, a good linearity is observed for
V T drift with temperature. This is not the case for the circular nanowire.
[(AV) 1/2 ]
Figure 4.11: (Left) A typical I D /g m 1/2 vs. VG linear dependence used for the extraction of the
threshold voltage. This methods allows an independent extraction of V T and μ 0 . (Right) Threshold
voltage V T dependence on temperature for a circular, triangular and Ω-gate device. Data extraction
and cross-section sizes correspond to measurements reported in Figures 4.3 to 4.8.
4.2.3 Mobility extraction and analysis
A scalability study of the extracted RT low field mobility as a function of the device cross section
dimensions is reported in Figure 4.12. The low field mobility is extracted using the slope of I D /g m 1/2
at V D =20mV. This is an accurate method that cancels the effect of series resistances [Ghi97].
A high mobility of ~850cm 2 /Vs is found in W eff =240nm (perimeter) size triangular cross-section
GAA devices 1 . Exact perimeter (device width) is evaluated by FIB cross-section performed on each
device after electrical measurement. This result is fully coherent with the comparison of the
normalized transconductance presented in Figure 4.9.
Figure 4.12: Experimental low-field mobility, μ 0 , for different device structures and dimensions.
SEM/TEM images are shown insets. A systematic inspections of measured devices provide accurate
data for the cross section dimensions (W eff ).
1. This work is carried out in collaboration with Kirsten E. Moselund [Mos06].

118 CHAPTER 4: Characterization and analysis
Moreover, in the fabricated 5nm-diameter cross-section wires, the mobility extracted (480cm 2 /Vs) is
very good and can be compared with up-to-date silicon nanowire geometries [Cui03]. This result is
attributed to the excellent crystallinity of the silicon core (in contrast to grown bottom-up
nanowires), to the quasi-circular uniformity of top-down fabricated nanowires and to the very good
quality of Si/SiO 2 interface. Another important origin of this unusual high value could be the circular
volume inversion and resulting displacement of the conductive channel from the Si/SiO 2 interface to
the center of the wire (dark-space ring). A description of volume inversion in GAA structures can be
found in [Mos06], and is also discussed in Chapter 2.
Mobility temperature dependence of the compared three devices is plotted in Figure 4.13. We
observe a mobility reduction at higher temperature due to the increased scattering in the silicon
lattice. An empirical model of mobility reduction is explained in [Bal01]. The temperature dependent
mobility can be expressed in the scattering regime (T>100K) as:
T
μ( T)
=
μ0⋅⎛----- ⎞
⎝ ⎠
T 0
– ξ
where μ 0 is the bulk mobility at T 0 =300K and ξ∼2.5 is a fitting factor depending of the carrier type.
Figure 4.13: Low-field mobility, μ 0 , dependence on temperature for three different cross-section size
devices. A maximum of mobility of 1802cm 2 /Vs is extracted at T=77K for the circular nanowire.
4.2.4 Enhanced carrier mobility due to PADOX strain
Concerning the high value of mobility extracted in triangular GAA wires (μ 0 =850cm 2 /Vs at RT), this
cannot be explained only by volume inversion which can appear in device corners [Mos06]. This is
rather attributed to the tensile stress in the wire.
Moreover, it is also worth mentioning that detailed simulations of corner effects show that their role
is less significant for low doped (N A

Gate-all-around MOS characterization 119
Normalized intensity
Wavenumber [cm -1 ]
center edge bulk
Location
Figure 4.14: (a) Raman spectrum measurement of a 20μm long nanowire at different positions. A
clear 5.90cm -1 downshift between the nanowire center and edge peak positions indicates that this
nanowire possesses 0.99% tensile strain. (b) A typical strain distribution measured by micro-Raman
spectroscopy along a silicon nanowire. (c) Strain value extracted from this device. The strain is
maximum in the center of the bent silicon nanowire, where the cross-section is the smaller.
The penetration depth of the λ=514nm Raman laser is approximately 760nm in silicon, therefore the
Raman signal could be controlled to distinguish the interaction of phonons and atoms from within the
nanowire from that of surrounding material. Raman spectra demonstrate that there is a non-uniform
strain distribution along the wire length. The maximum value of strain occurs at the centre of the
wire and decreases towards the support at the nanowire ends. The substrate, support and material
close to the nanowire do not exhibit any strain.
Data in Figure 4.15 show the predicted trends from strain as a function of nanowire length and width
using simple statistical and linear relations from 10 devices measurements. Tensile strain clearly
increases with both increasing nanowire length and decreasing nanowire width.
Strain value, S [%]
(a)
(b)
Wire width, W eff [μm]
Figure 4.15: Strain dependence on nanowire length and on designed (lithographic) widths that
correspond to bent wires for all widths smaller than 1.8μm.
The relative increase of μ 0 in GAA MOSFET due to tensile stress shows an increase of the piezoresistive
coefficient when the temperature decreases, resulting in a higher mobility gain at low
temperatures, as predicted by piezo-resistance theory reported in [Kan82]. At room temperature, a
mobility increase up to 40% is measured in the strong inversion regime, with built-up tensile stresses
ranging from 200MPa to 2GPa in nanowire transistors. The absolute measurement error is 15MPa. In
the weak inversion regime, mobility enhancement up to 90% is observed.
Finally, as strain is necessary in the formation of SET islands in a silicon wire (bandgap reduction),
then Raman measurements strongly support PADOX occurrence in our nanowires (see Figure 2.7).
Strain value
8%
6%
4%
2%
0%
Wire length, L [μm]
(c)

120 CHAPTER 4: Characterization and analysis
4.3 Cryogenic local-SOI devices characterization
4.3.1 Coulomb oscillations and Coulomb gap
Cryogenic temperature (4.5K

Cryogenic local-SOI devices characterization 121
Apart from a V G offset, repeated measurements plotted in Figure 4.17 are reproducible in terms of I D
peaks height and periodicity. The maximum I D peak current reached is about 10pA, which is
consistent with other recent results on single electronics [Lee06]. The associated transconductance is
also plotted and shows a typical CB evolution; in the range of 10 -5 to 10 -6 in units of e 2 /h.
Fast Fourier Transform (FFT) was performed (with data from Figure 4.17) to extract the power
spectrum density (Figure 4.18). This gives an estimation of the power associated with each
periodicity in the I D -V G curve. The dispersion around the central value is probably due to the
modulation of the electrostatically defined channel [Boe03] and is discussed in the next section. In
addition, I D peak current change in Figure 4.17 could be induced by a dependency with V G of the
tunnel barriers height.
Periodicity, ΔVG [mV]
Figure 4.18: Power Fast Fourier Transform (FFT) of measured characteristics from Figure 4.17.
Peak periodicity is ranging from 10 to 30mV over 8 oscillations. The associated gate capacitance
C G =e/ΔV G is ranging from 6 to 16aF. The very low value of Power FFT for V G 500nm) or for
T>20K.
Figure 4.19: Low temperature I D -V D characteristics of a triangular GAA transistor showing a
Coulomb blockade gap of 20mV for T

122 CHAPTER 4: Characterization and analysis
The next plot, in Figure 4.20, is another measurement performed on a L=1.2μm GAA triangular
device. The progressive disappearance of the oscillating regime in weak/moderate inversion is
clearly observed. At T=20K, no oscillations are visible, which is coherent with other oscillating
device measurement and with the literature (see Figure 2.13).
Figure 4.20: I D -V G thermal dependent characteristics of a triangular gate-all-around transistor. The
channel length is 1.2μm and the gate oxide thickness 20nm.
The Figure 4.21 shows the impact of the drain bias V D on oscillating characteristics. A drain bias
smaller than 10mV, is needed to increase the oscillating current behavior, which is fully coherent
with the orthodox theory (see Section 1.5.2). As a comparison, kT/q=0.86mV at T=10K. The V D gap
range is in agreement with the I D -V D Coulomb gap measured in Figure 4.19.
Figure 4.21: I D -V G characteristics of a triangular gate-all-around transistor, for different drain
biases. The channel length is 1.2μm and the gate oxide thickness 20nm. Oscillations are observed at
low V D bias and in the weak/moderate inversion regime.
In summary, devices integrated with the gate-all-around local-SOI technology (Section 3.4) are
exhibiting I D -V G oscillations and an I D -V D conduction gap, at a temperature of T

Cryogenic local-SOI devices characterization 123
These conditions result from the observation of the different tested devices. Unfortunately, it was not
possible to probe device at a temperature lower than liquid He (T=4.5K). However, an interesting
measure is the characterization of a 5nm diameter silicon nanowire device. Despite its very reduced
cross-section, this device is not oscillating at all. The curve is plotted in Figure 4.22.
Figure 4.22: I D -V G characteristics of a 10μm GAA transistor, measured at T=4.5K and at very low
drain bias. The gate oxide thickness is 10nm and the equivalent width 16nm. This device corresponds
to the TEM image in Figure 3.33.
The output characteristic of the same device is represented in Figure 4.23. In accordance with the
previous measurement (Figure 4.22), this device does not show any Coulomb gap at low
temperature. Only a tiny kink effect is observed and is discussed in the Section 4.3.3.
Figure 4.23: On the right, output characteristics (I D -V D ) of a 10μm circular GAA transistor,
measured at T=4.5K. The gate oxide thickness is 10nm and the equivalent width 16nm. The inset on
the left represents the same device measurement, at a different scale. This device corresponds to the
TEM image in Figure 3.33.
4.3.2 Cryogenic measurement analysis
Linear
regime
The previous section reports cryogenic measurements observed. The analysis is split in two parts.
First, device parameters are extracted with orthodox theory formalism, and the possible origin of
SET island and tunnel barriers are discussed. The orthodox theory is an ideal SET model, but is not
perfectly suited for silicon-based devices.
At the contrary, the second analysis based on 1D-quantum sub-bands formation is a true physical
approach. This models describe irregular I D -V G oscillations observed in the conductance of a 1D
silicon nanowire. Finally, the validity of each approach is discussed, references are given and an
optimization of the CB regime is proposed.
kink

124 CHAPTER 4: Characterization and analysis
Orthodox theory parameter extraction
If we consider I D -V G plots in Figure 4.17 or in Figure 4.20, then we observe two regions, depending
on the channel inversion level - controlled by the gate bias:
(i) Depletion to weak inversion: we observe oscillations with an average
period of 20mV. The V G range with oscillating characteristics is about
100mV to 200mV. The maximum number of periods observed is 8.
(ii) Strong inversion: the device has a pure FET behavior (no oscillations).
In standard orthodox theory [Lik99], a single electron transistor consists in a conductive quantum dot
connected to two reservoirs through opaque tunnel junctions. Even though the design of a thin barrier
is a big technological challenge, some reports have shown CB oscillations in structures without
intentional barriers (see Section 2.2). To explain this, it is suggested (see Figure 2.7) that a nanoscale
silicon constriction combined with stress non-uniformity leads to tunnel barriers along the length of
the channel [Tak00]. It is interesting to note that the height of these unintentional tunnel barriers
could be dependent on V G . For example, a decrease of tunnel barrier resistance could explain the
disappearance of the oscillations in strong inversion regime.
The proposed theory to explain SET behavior can be supported by the fact that the oxidation induced
stress, which lowers the bandgap in the middle of the wire [Tak04], is maximum in the center of the
wire. This is coherent with Raman strain measurement presented in the section 4.2.4. Therefore, at
low V G the conducting channels could be formed in a potential well which would provide lateral
tunnel barriers for SET operation. The role of corners is essential, as only triangular devices exhibit
CB at T>4.5K. However, as V G increases, inversion takes place in the whole wire and the tunnel
barriers disappear. This means that the device behaves as a FET in the strong inversion regime.
Moreover, in addition to the lateral confinement we deduce that further localization occurs in the
length of the wire. This explains the low value of C G (typically 8 to 16aF, for measurement reported
in Figure 4.17) extracted from the measured CB oscillations.
Device parameters were extracted from best measurements (Figure 4.17) and fitted by using Monte-
Carlo simulation (see Section 1.5.2). We found the following values: C G =16aF, C D =C S =4aF and
R D =R S =10MΩ. This fit was calculated over 8 oscillation periods and is not taking into account the
dependency of R D and R S with V G .
Altogether, we propose a parametric equivalent model (see Figure 4.24) for a GAA triangular device
that consists in a SET based on analytical modeling developed on orthodox theory [Lik99], in
parallel with a FET based on EKV compact theory [Sal03].
Figure 4.24: (a) I D -V G model based on an a SET-FET current superposition. The total device current
is simply modeled by making the sum of SET and FET contributions. SET simulation parameters are
C G =16aF, C D =C S =4aF and R D =R S =10MΩ. FET simulation is using the following parameters:
W eff =120nm, L=1μm and t ox =40nm. (b) Equivalent circuit schematic corresponding to a triangular
cross-section. (c) Device cross-section. (d) TEM cross-section of a triangular device.
VD
ID
VG
VS
FET
Gate
oxide
(d)
(a) (b) (c)
VG
Si
Corner
(SET dot)

Cryogenic local-SOI devices characterization 125
The total device current is I nanowire =I SET +I FET . Such an approach has still been proposed, for
example by B. Naser in [Nas03]. The advantages of this equivalent model are:
• An extreme simplicity.
• A full de-coupling between SET and FET theory.
• A continuous expression from weak to moderate and strong inversions.
• An easy fit between measurements and modeling.
For a negative V G voltage (depletion/accumulation), the wire is blocked and the current should be set
to I OFF value (

126 CHAPTER 4: Characterization and analysis
The function f FD (E) represents the familiar Fermi-Dirac distribution:
fFD( E)
1 + e
E– EF --------------kT
This model was preliminary executed for a triangular cross-section and at room temperature. The
simulation of the energy distribution as a function of the product of DoS and Fermi-Dirac
distribution is represented in Figure 4.25. The two curves plotted represent a comparison between a
classical Poisson model (3D electron-gas) and a combined Schroedinger-Poisson model (1D
electron-gas). The mean difference between the discreet levels E j for such a cross-section and at
room temperature are much smaller than the thermal energy kT=25.9meV. This means that no
significant oscillating characteristics will be observed on measured characteristics (see Figure 4.16).
Figure 4.25: Simulation of a 3D and 1D electron energy distribution performed on a triangular crosssection.
1D singularities are resulting from quantum confinement in the structure. The gate voltage is
set at V G=V FB and the temperature is T=300K. At an energy level above ~6kT from the conduction
band E c0, the electron population is almost negligible.
The smaller the cross-section, and the higher the difference between two successive sub-bands. A
smaller cross-section is much more sensitive to one-dimensional quantum sub-bands formation.
30nm
-----------------------
1
=
Energy distribution, Ec [eV]
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
-0.02
45nm
BOX
3D distribution
Figure 4.26: Finite element meshing.
1D distribution
30nm
Density of states x Fermi-Dirac distribution, [cm -3 eV -1 ]
Gate
oxide
45nm
T=300K
VG=VFB
With the generated mesh structure, then it is possible to calculate the electron concentration n(x,y) at
any gate voltage, by using the Equation 4.5.
~6kT=0.16eV
Si
T ox=20nm
Conduction band: Ec0
x10 -7
(4.6)
The Figure 4.26 represents the finite element
meshing generated by COMSOL for the
simulation. A thin buried oxide must be
preserved, but this has a negligible impact on the
results.
In order to limit the processing time, the number
of elements should be as reduced as possible.
Indeed, in a self-consistent coupled Poisson-
Schroedinger simulation, two different solvers are
needed: a linear solver for the Poisson equation
and a eigen-values solver for the Schroedinger
equation. This means also that full 3D simulation
is extremely time consuming.

Cryogenic local-SOI devices characterization 127
The Figure 4.27 shows the electron distribution in a triangular wire biased in the strong inversion
regime. Three peaks appear in the corners of the structure. This cross-section size is fully depleted in
the strong inversion mode. See Section 2.4.2 for a comparison with Density-Gradient simulation.
Figure 4.27: Poisson-Schroedinger electron concentration simulation in a GAA triangular crosssection,
for an applied voltage of V G=0.5V and at T=300K.
The total current in the wire is calculated with the Equation 4.7. The validity of this equation is
limited to long channel devices (L>500nm) and at low drain bias (V D

128 CHAPTER 4: Characterization and analysis
The same model could be theoretically used at very low temperature (T

Cryogenic local-SOI devices characterization 129
The CB behavior discussion is summarized on Table 4.2. This concludes the discussion on the origin
of Coulomb oscillations. The general conclusion is proposed in Chapter 5.
TABLE 4.2: OSCILLATIONS ORIGIN HYPOTHESIS AND DISCUSSION.
Models Pro Opposite Ref
Role of the
corners
1D quantum
sub-bands
formation
PADOX:
strain
engineering
Impurities
and
scattering
• Coulomb Blockade observed in
triangular wires only.
•I D -V G oscillations measured.
•I D -V D gap measured.
• Coherent with the MOS coupled
effect observed.
• Coherent with physics and
modeling.
• Very small cross-section.
• May explain irregular oscillations
observed.
• Strain level measured by micro-
Raman spectroscopy.
• Strain combined with 1D-confined
results in a quantum well in the
center of the wire (PADOX, see
Chapter 2).
• The smaller the cross-section, and
the higher the strain.
• May also explain irregular
oscillations.
4.3.3 Kink effect in local-SOI devices
• A localization along the length of
the wire should be highlighted.
• No oscillations observed in circular
nanowires (L=10μm, d=5nm).
• Variations of dimensions along the
length of the wire may result in a
variation of the DoS.
• Does not explain the I D -V D
Coulomb gap measured.
• The wire length is long compared to
a typical SET island.
[Pot06b]
[Pot06c]
[Nas03]
[Col06a]
[Col06b]
[Col06c]
[Dav98]
[Gre90]
[Mos07a]
[Dob05]
[Tak00]
• No analysis of highly doped wire. [Eva01]
At low temperature (T

130 CHAPTER 4: Characterization and analysis
At room temperature, no kink has been observed, for V DS 11V) on
transistors that have a short channel (L=0.9 to 10μm).
This impact ionization effect can be exploited to abruptly switch from low to high current (2 decades
of current) states of I D -V G characteristics with ultra-abrupt slopes of 5 to 10mV/dec.
At low temperature, impact ionization is clearly described in [Bal01]. In our GAA devices, the
successive physical effects that appear are shown in Figure 4.31.
Wire
Fully depleted
region
Deposited oxide
Bulk p-Si
IDS
IDS
Impact
ionization
Drain
n+
Figure 4.31: Schematic of the neutral p-type pocket in a GAA transistor. At high V DS , holes are
polarizing this pocket and forward biasing this region. This results in a lower V T for the all-around
channel, and so a net I D increase.
The low temperature reduces the current leakage from the p-type pocket to drain and increases also
the resistances of this pocket (freeze-out of dopants). As a result, the kink effect occurs at lower V DS
and is observed with a steeper slope in the I D -V D characteristics.
However, this impact ionization effect does not affect the performances in our devices, as it is turned
ON only at high values of V D . It was only proposed as additional information.
e-
e-
x
h +
h +
x
Impact
ionization
VDS increase
p-Si
Electric field EDS increase
Impact ionization
h + in the neutral region
Self-polarization of neutral
region
Equivalent VT drop
ID current increase
n+

SOI transistors 131
4.4 SOI transistors
4.4.1 Room temperature characterization
Gate-all-around nanowires have been produced on SOI wafers. The complete process flow is
presented in the Section 3.5. This characterization part presents measurements and discussed the
performances of the devices. Compared with local-SOI devices on bulk silicon, the integration and
control of dimensions on SOI is even more difficult. However, advantages of the fabricated SOI
wires are a reduced channel length (polysilicon under-etch), a 10nm thin gate oxide, RTA activated
dopants and no bulk current leakage.
First curves proposed are I D-V G and I D-V D measurements of a planar W/L=2μm/2μm SOI device
(see Figure 3.41). The SOI thickness in the active region is 40nm, inducing a fully-depleted
operating mode [Kuo98].
VFB
Figure 4.32: Room temperature I D -V G (left plot) and I D -V D (right plot) characteristics of a 2μm x
2μm SOI device. The bulk bias is grounded during measurement.
The analysis of the curves presented in Figure 4.32 is:
VT
S=300mV/dec
S=330mV/dec
S=120mV/dec
• This device is a gate-all-around transistor but behaves rather as a single gate SOI
MOSFET with the second gate non-implanted. Indeed, the polysilicon below the gate is
not or partly doped. This blurring effect is the same as the one presented for the Ω-gate,
in Figure 3.36.
•The I OFF current is very low (

132 CHAPTER 4: Characterization and analysis
• The cross-section of SOI devices is rectangular, even for small cross-sections
dimensions, as shown in Figure 4.33.
• S/D contacts are ohmic. Neither self-heating, nor a kink are observed on room
temperature I D -V D characteristics.
Small cross-section SOI devices have also been investigated. The device is first measured and then
cut by FIB milling. It corresponds to the device shown in Figure 4.33.
BOX
SOI pad (D)
SOI pad (S)
Figure 4.33: SEM pictures of a 300nm long SOI nanowire transistor. On the left, a tilted view of the
device is shown. On the right, the same device after FIB cut is displayed. The buried oxide could not
have been kept during the process, and a very thin 10nm oxide (gate oxide growth) is insulating the
silicon bulk from the polysilicon.
Room temperature I D -V G characteristics of the device of Figure 4.33 is proposed in Figure 4.34.
Compared with a large cross-section, a reduced I ON current is measured. The subthreshold swing is
divided into two sections: the first part at low V G with a steeper slope and a second with a reduced
swing. This could be explained by the strong impact of the handle wafer acting as a second gate.
The effective width of this device is not the perimeter of the channel cross-section, because the
polysilicon below the SOI is un-doped (LPCVD polysilicon). The SOI gate doping (arsenic + RTA)
strongly differs from the local-SOI gate process (phosphorus + thermal annealing).
Figure 4.34: I D -V G characteristics of a 300nm SOI nanowire transistor. The top wire width is about
500nm.
We conclude as followed:
FIB cut
Gate
Pt Silicon
Gate (poly-Si)
SiO 2 (10nm)
4μm
Si-bulk
500nm
• From measurements of Figure 4.34, it was extracted I ON =4.6nA/nm at V G -V T =2V and
V D =1V. This is a very low value.

SOI transistors 133
• It seems difficult to explain the low current drive of SOI nanowires, because larger
transistors integrated on the same wafer are showing good characteristics. This could, for
instance, be attributed to the uncertainty over W and L dimensions.
• The worst case access resistance of SOI nanowires has been calculated. This considers a
uniformly n+ doped (10 -3 Ωcm) conductive layer, with a junction depth x j =50nm, a width
of 500nm and a length of 3μm. This results in R ACCESS =1.2kΩ. This value cannot
explain the very low current measured.
• The subthreshold behavior is slightly improved in comparison with larger transistors.
The I D -V D characteristics of the same device are plotted in Figure 4.35.
Figure 4.35: I D -V D characteristics of a L=300nm and W=500nm SOI nanowire.
In order to highlight the effect of the bulk polarization, the same SOI nanowire has been measured
with 3 different handle wafer bias values, as reported in Figure 4.36. A large positive bias increases
the drain current by a factor of 2.5 in the strong inversion regime, compared to a grounded bulk.
Figure 4.36: The impact of the handle wafer bias on the current output for an SOI nanowires device,
the same as the one measured in Figure 4.34 and 4.35.
Despite many small SOI devices characterization, the origin of such a reduced current level is still
not clearly explained. However, the feasibility of SOI nanowires is shown, even if devices size,
structure and performances should be highly improved.

134 CHAPTER 4: Characterization and analysis
4.5 Summary
4.5.1 Synopsis
We proposed the following in this chapter:
• Room temperature local-SOI MOS characteristics (Section 4.2)
Excellent room temperature characteristics are demonstrated. We observed a good
control of the threshold voltage and a close-to-ideal subthreshold slope of 70mV/decade.
Depending on wire shape and dimension, it was found a maximum of 850cm 2 /Vs lowfield
mobility for mid-range triangular cross-section size. Furthermore, the mobility in
ultra-scaled silicon nanowires is good, in contrast with the circular 5nm diameter of the
device.
Enhanced carrier mobility is explained by strain induced during silicon oxidation. Bent
nanowires exhibit a shifted Raman spectrum, which demonstrates tensile strain in the
center of the wire and so explain the large value of mobility measured. Statistic analysis
on wire length and cross-section size shows a maximum accumulated strain on smallest
cross-sections.
• Local-SOI MOS-SET hybrid characteristics at low temperature (Section 4.3)
We measured at cryogenic temperature short silicon wires (L

Bibliography 135
4.6 Bibliography
[Bal01] ’’Device and circuit cryogenic operation for low temperature electronics’’, edited by F. Balestra and
G. Ghibaudo, Kluwer academic publisher, ISBN 0-7923-7377-4, 2001.
[Boe03] F. Boeuf, X. Jehl, M. Sanquer and T. Skotnicki, ’’Controlled single-electron effects in
nonoverlapped ultra-short silicon field effect transistors’’, IEEE Transactions on Nanotechnology,
vol. 2 (3), pp.144-148, 2003.
[Coa07] http://www.microwaves101.com/encyclopedia/coaxdual.cfm (2007)
[Col06a] J.-P. Colinge, L. Floyd, A. J. Quinn, G. Redmond, J. C. Alderman, X. Xiong, C. R. Cleavin, T.
Schulz, K. Schruefer, G. Knoblinger and P. Patruno, ’’Temperature effects on trigate SOI
MOSFET’’, Electron Device Letters, vol. 27 (3), pp. 172-174, 2006.
[Col06b] J.-P. Colinge, A. J. Quinn, L. Floyd, G. Redmond, J. C. Alderman, W. Xiong, C. R. Cleavelin, T.
Schulz, K. Schruefer, G. Knoblinger and P. Patruno, ’’Low-temperature electron mobility in trigate
SOI MOSFETs’’, Electron Device Letters, vol. 27 (2), pp. 120-122, 2006.
[Col06c] J.-P. Colinge, J. C. Alderman, W. Xiong and C. R. Cleavelin, ’’Quantum-mechanical effects in
trigate SOI MOSFETs’’, Transactions on Electron Devices, vol. 53 (5), pp. 1131-1136, 2006.
[Cui03] Y. Cui, Z. Zhong, D. Wang, W. U. Wang and C. M. Lieber, ’’High performance silicon nanowire
field effect transistors’’, Nano Letters, vol. 3 (2), pp. 149-152, 2003.
[Dav98] J. H. Davies, ’’The physics of low-dimensional devices’’, Cambridge University Press, UK, 1998.
[Dob05] P. Dobrosz, S. J. Bull, S. H. Olsen and A. G. O’Neill, ’’The use of Raman spectroscopy to identify
strain and strain relaxation in strained Si/SiGe structures’’, Surface and Coatings Technology, vol.
200 (5-6), pp. 1755-1760, 2005.
[Eva01] G. J. Evans, H. Mizuta and H. Ahmed, ’’Modelling of structural and threshold voltage characteristics
of randomly doped silicon nanowires in the Coulomb-Blockade regime’’, Japanese Journal of
Applied Physics, vol. 40, pp. 5837-5840, 2001.
[Ghi88] G. Ghibaudo, ’’New method for the extraction of MOSFET parameters’’, Electronics Letters, vol. 12
(9), pp. 543-545, 1988.
[Ghi97] G. Ghibaudo, ’’Critical MOSFETs operation for low voltage/low power IC's: Ideal characteristics,
parameter extraction, electrical noise and RTS fluctuations’’, Microelectronic Engineering, vol. 39
(1-4), pp. 31-57, 1997.
[Gre90] M. A. Green, ’’Intrinsic concentration, effective densities of states, and effective mass in silicon’’,
Journal of Applied Physics, vol. 67 (6), pp. 2944-2954, 1990.
[Hof05] M. Hofheinz, X. Jehl, M. Sanquer, G. Molas, M. Vinet and S. Deleonibus, ’’Detection of individual
traps in silicon nanowire transistors’’, Proceedings of ESSDERC, pp. 225-228, Grenoble FR, 2005.
[Kan82] Y. Kanda, ’’A graphical representation of the piezoresistance coefficients in silicon’’, Transactions
on Electron Devices, vol. 29, pp. 64-72, 1982.
[Kuo98] J. B. Kuo and K.-W. Su, ’’CMOS VLSI Engineering Silicon-on-Insulator (SOI)’’, Kluwer Academic
Publishers, Dordrecht NL, 1998.
[Lee06] W. Lee, P. Su, H.-Y. Chen, C.-Y. Chang, K.-W. Su, S. Liu and F.-L. Yang, ’’An assessment of singleelectron
effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature’’,
Electron Device Letters, vol. 27 (3), pp. 182-184, 2006.
[Lik99] K. K. Likharev, ’’Single electron devices and their applications’’, Proceedings of the IEEE, vol. 87
(4), pp. 606-632, 1999.
[Mos06] K. E. Moselund, D. Bouvet, L. Tschuor, V. Pott, P. Dainesi and A. M. Ionescu, ’’Local volume
inversion and corner effects in triangular gate-all-around MOSFETs’’, Proceedings of ESSDERC,
pp. 359-362, Montreux CH, 2006.
[Mos07a] K. E. Moselund, P. Dobrosz, S. Olsen, A. O’Neill, L. De Michielis, V. Pott, D. Tsamados and A. M.
Ionescu, ’’Bended gate-all-around nanowire MOSFET: a device with enhanced carrier mobility due
to oxidation-induced tensile stress’’, Technical Digest of IEDM, Washington DC, 2007.
[Mos07b] K. E. Moselund, V. Pott, D. Bouvet and A. M. Ionescu, ’’Abrupt current switching due to impact
ionization effects in Ω-MOSFET on low doped bulk silicon’’, Proceedings of ESSDERC, pp. 287-
290, Munich DE, 2007.

136 CHAPTER 4: Characterization and analysis
[Nas03] B. Naser, K. H. Cho, S. W. Hwang, J. P. Bird, D. K. Ferry, S. M. Goodnick, B. G. Park and D. Ahn,
’’Transport study of ultra-thin SOI MOSFETs’’, Physica E: Low-dimensional Systems and
Nanostructures, vol. 19 (1-2), pp. 39-43, 2003.
[Pot06a] V. Pott, D. Bouvet, K. E. Moselund and A. M. Ionescu, ’’Carrier mobility in ultra-scaled gate-allaround
silicon nanowires’’, International Conference on Nano Science and Nano Technology (GJ-
NST), Gwangju KO, 2006.
[Pot06b] V. Pott, D. Bouvet, J. Boucart, L. Tschuor, K. E. Moselund and A. M. Ionescu, ’’Low temperature
single electron characteristics in gate-all-around MOSFETs’’, Proceedings of ESSDERC, pp. 427-
430, Montreux CH, 2006.
[Pot06c] V. Pott, J. Boucart, D. Bouvet, K. E. Moselund and A. M. Ionescu, ’’Coulomb blockade in gate-allaround
silicon nanowire MOSFETs’’, Proceedings of IEEE Silicon Nanoelectronics Workshop, pp.
25-26, Honolulu HI, 2006.
[Sal03] J.-M. Sallese, M. Bucher, F. Krummenacher and P. Fazan, ’’Inversion charge linearization in
MOSFET modeling and rigorous derivation of the EKV compact model’’, Solid-State Electronics,
vol. 47 (4), pp. 677-683, 2003.
[Tak00] Y. Takahashi, A. Fujiwara, Y. Ono and K. Murase, ’’Silicon single-electron devices and their
applications’’, Proceedings of ISMVL Conference, pp. 411-420, Los Alamitos CA, 2000.
[Tak04] Y. Takahashi, Y. Ono, A. Fujiwara and H. Inokawa, ’’Silicon single-electron devices and their
applications’’, Proceedings of ICSICT Conference, vol. 1, pp. 624-629, Beijing CN, 2004.

Chapter 5
Conclusion and perspectives
At the end comes the conclusion. Both strengths and limitations of this thesis are given.
Perspectives are also proposed, including some personal views.

138 CHAPTER 5: Conclusion and perspectives
5.1 Major achievements in this work
The main contributions of this work have been divided in two distinct levels: the MOS part and the
SET part, as suggested in Figure 5.1. The two devices are explored supposing their integration on an
identical structure: the silicon nanowire.
STOP
Problematic
End of Moore’s law
Short channel effect
Power consumption
Which ITRS roadmap ?
Integration cost
Figure 5.1: From a problematic, we developed a single solution for two complementary applications.
The major achievements of this thesis can be summarized as:
One solution: GAA
silicon nanowires
A single low cost technology
Many dimensions and shapes
Nanoscale channel section
Application 1: MOS Application 2: SET
Enhanced carrier mobility
Strained silicon
Low IOFF and High I ON
• We proposed and tested different technologies for the integration of silicon nanowires.
The most successful was the gate-all-around nanowire processing on bulk silicon, and
was presented in Section 3.4.
Despite some limitations, we have obtained silicon nanowires with various cross-section
shapes and dimensions. A minimum of 5nm in the diameter of a circular wire has been
observed (See Figure 3.33). The merit of this cross-section dimension, compared with
state-of-the-art silicon nanowires, was highly encouraging. Advantages of the top-down
developed process are (i) a prefect localization of the wires, (ii) a control of the doping
level and of the crystalline orientation, (iii) very good ohmic contacts and (iv) an
excellent yield and reproducibility over the wafer. Furthermore, the global cost of the
process was very low. The scalability of this process was discussed and was shown to be
excellent.
At the opposite, the gate stack integration, made of undoped polysilicon, may lead in lost
in the channel electrostatic control and should be improved.
• Static measurements of GAA MOSFET are reported and interpreted. Characteristics are
presented, including the extraction of the threshold voltage and of the subthreshold
slope. Furthermore, micro-Raman measurement has shown enhanced electron mobility
(up to μ n =850cm 2 /Vs at RT) due to process-induced strain in the wire.
• Cryogenic measurements (T

Perspectives 139
5.2 Perspectives
This second section is a discussion on CMOS/SET hybrid technology perspectives, based on the
author’s experience during the Ph.D. work and his personal point of views. This thesis report has
deliberately presented all the technologies considered during the 4-year of this work, and failures in
some processes are shown 1 and analyzed. However, the main conclusion is that a clear feasibility of
an hybrid CMOS/SET technology has been demonstrated.
In the future of hybrid CMOS/SET integration, we propose the following comments:
• The lateral pattern definition (LPD) technique is interesting and deserves more
investigation. Some nice realizations using LPD techniques have been proposed.
• At the opposite, FIB direct milling may help for the prototyping of single devices (if the
gallium contamination problem is efficiently addressed), but is useless at large scale
integration.
• A much better photolithography system has to be use. It is a «dream» to believe that sub-
10nm dimensions can be achieved in a controlled and reproducible way with a 0.8μmresolution
optical system.
• Silicon etching performances 2 have also to be drastically increased, compared to what
was used in this work. Low speed anisotropic silicon etch, with low roughness sides, is
absolutely mandatory.
• New dielectric layers (currently limited to ~10nm SiO 2 as gate oxide) have to be
introduced. High-k dielectrics seem also to be an appealing option.
• The use of SOI wafers is not a so good idea. Many process difficulties are introduced and
the increase in performances is still not clearly demonstrated.
• The channel length of the nanowires has to be reduced. This will increase ON-current of
MOS transistors and also helps to turn ON the low temperature single electron transistor
mode. The numbers of oscillations has to be increased, as well as their regularity. The
SET operating temperature is still very low. An hybrid technology supposes the use of
MOS and SET transistors on the same chip and at the same temperature.
• Enhanced carrier mobility measured by Raman spectroscopy shows a process-induced
strain. Stress due to oxidation will be a major booster at nano-scale. In this thesis, we
proposed initial measurement. Further studies are needed, like full 3D oxidation
modelling.
• There is still a lack of a realistic model of silicon-based single electron transistors.
Without a compact model, the viability of any new technology is highly compromised.
• Basic electronic cells including hybrid integration of both MOS and SET devices have
still been demonstrated. However, performances are limited and the functional
temperature is low. As long as a reliable SET working at room temperature has not been
realized, further hybrid circuit research seems useless. The effort has to be pushed on
technology first.
Final questions, that the author is not going to answer in this report, are on the future of single
electronics 3 .
Which SET geometry is the best? Which technology should be developed now? What is the price
that the market is ready to pay for that? Is the PADOX a good solution? How can we really isolate
and control the conduction through a 1nm quantum dot? What are the solutions proposed by a
bottom-up approach? Should we either go back to non-silicon SET? etc.
Many efforts have been pushed for about 20 years in the development of emerging devices for
CMOS replacement. Surprisingly, the CMOS itself, seems currently the nano-device to be the most
promising! A very interesting and uncertain nanoelectronic time will happen in the next years...
1. I had rather be hissed for a good verse than applauded for a bad one. Victor Hugo, French Writer, 1802-1885.
2. See: http://cmi.epfl.ch/
True nanoelectronic projects require extremely high technology standards, that unfortunately are rarely
accessible in an academic cleanroom.
3. ACTA EST FABULA. (The show is finished). Latest words of Augustus, Roman Emperor (63 BC - 14 AD).

Appendix A 141
APPENDIX A: PBL AND SOI OXIDATION
In this appendix, we describe in details the process and simulation used to locally or completely thin
down SOI wafers. SOI thinning is essential to reduce the channel cross-section of silicon nanodevices.
This was used, for example, in the sketch presented in Figure 3.19.
The Polysilicon-Buffered LOCOS (PBL) was preliminary developed as a technique of isolation
between devices. LOCOS stands for local oxidation of silicon. There are many examples in the
literature of LOCOS, PBL and their variants. Authors have proposed optimizations for low stress and
low impact on integrated devices 1 or for a small bird’s beak extension 2 . LOCOS, as a device
isolation technique, is more and more replaced by STI (shallow trench isolation) 3 , which is better for
ultra high density integration.
We have adapted the PBL technique, for the use in the Section “Focused ion beam prototyping” on
page 90. We have integrated a polysilicon layer before silicon oxidation in order to decrease the
oxidation-induced stress in the underneath SOI layer and to limit lateral bird’s beak extension. The
one we choose is very simple, easily controllable and can be optimized by process simulation. We
also choose to avoid the commonly used LPCVD nitride layer, because the access to an etchant bath
to selectively remove nitride layer (phosphoric acid at T=160°C) is not available.
The figures presented below show our PBL process.
SOI 110nm
Buried oxide: 400nm
Handle wafer
Figure A1: SOI wafer with 110nm of boron
low-doped silicon and 400nm of BOX.
Figure A3: Photolithography, anisotropic dry
etch of polysilicon and resist removal.
SiO 2 20nm + Poly 50nm
Figure A2: Thermal growth of 20nm of oxide
and 50nm LPCVD polysilicon deposition.
500nm Bird’s beaks
Figure A4: T=1050°C silicon oxidation under
O 2 atmosphere after 60 minutes.
1. C.-L. Huang, H. R. Soleimani, G. J. Grula, J. W. Sleight, A. Villani, H. Ali and D. A. Antoniadis, ’’LOCOS-Induced
stress effects on thin-film SOI devices’’, IEEE Transactions on Electron Devices, vol. 44 (4), pp. 646-650, 1997.
2. Se-Aug Jang, Chung-Soo Han, Young-Bog Kim and In-Seok Yeo, ’’The role of polysilicon film in the suppression of
bird’s beak in Poly-Buffered LOCOS’’, IEEE Transactions on Electron Devices, vol. 46 (2), pp. 433-436, 1999.
3. P. Van Der Voorn, D. Gan, and J. P. Krusius, ’’CMOS Shallow-Trench-Isolation to 50-nm channel widths’’, IEEE
Transactions on Electron Devices, vol. 47 (6), pp. 1175-1182, 2000.

142 Appendix A
Figure A5: T=1050°C silicon oxidation under
O 2 atmosphere after 120 minutes. The
polysilicon is fully oxidized.
Figure A7: T=1050°C silicon oxidation under
O 2 atmosphere after 240 minutes.
Figure A6: T=1050°C silicon oxidation under
O 2 atmosphere after 180 minutes.
Figure A8: Oxide etch in a BHF bath. The
central part of SOI is reduced to 30nm.
Our process has also the advantage to limit the stress in the active SOI layer. In the bird’s beak zone,
the strain is mainly concentrated in the polysilicon buffer layer. This avoids uncontrolled strain in
silicon, which can lead to tens of percent of mobility lost, depending on silicon doping and
crystalline orientation. The Figure 9 represents a stress simulation during the PBL process, with a
maximum stress concentration in the polysilicon layer.
110nm
y
Polysilicon
SOI
BOX
High stress
region
SiO 2
Thin SOI
Stress Sxy
[GPa]
Figure A9: Sxy stress simulation in a PBL structure, corresponding to step process of Figure 4. The
minus sign means a compressive strain, while a positive strain is represented with a positive value.
The finite elements mesh is also represented. A non-linear viscoelastic model 1 x
of silicon oxidation
was used, including a stress-dependent oxidation rate.
1. DIOS Synopsys TCAD tool, release 10.0. See: http://www.synopsys.com/products/tcad/dios_ds.html
70nm
-1
-0.5
0
0.2
0.4
0.6

Appendix A 143
We made also different types of silicon oxidation. The plots presented in Figure 10 and Figure 11 are
showing simulation results of wet and dry oxidation, respectively. These results have been used to
thin down SOI wafers.
The wet oxidation is characterized by a high oxidation rate, but suffers from a much lower precision
in the oxide growth control. Wet oxidation is operated at high temperature (typically from 900°C to
1050°C) under vapor atmosphere:
Si + 2H2O → SiO2 + 2H2 Figure A10: Wet oxidation at T=1000°C for a boron low-doped (10 13 cm -3 ) SOI wafer. Oxidation gas
flows in the oxidation tube are 16l/min for H 2 and 8.3 l/min for O 2. After t=150min, the SOI
thickness is reduced from 343nm to 21nm and a SiO 2 layer of 712nm is grown.
The dry oxidation has much slower oxidation growth but is much better controlled. The quality and
density of the resulting oxide is excellent. This was used to thin down SOI wafers with a high
precision. The dry oxidation chemical reaction is the following:
Si + O2 → SiO2 Thickness [nm]
Thickness [nm]
1200
1000
800
600
400
200
600
550
500
450
400
350
SOI
Initial SOI thickness: 343nm
0
0 20 40 60 80 100 120 140 160
SOI
Figure A11: Dry oxidation simulation at T=1050°C for a SOI boron low-doped (10 13 cm -3 ) wafer.
The O 2 oxidation gas flow in the oxidation tube is 10l/min. After t=180min, the SOI thickness is
reduced from 96nm to 7nm and a SiO 2 layer of 188nm is grown.
The two simulations made are very accurate. The typical error between measurement and simulation
is ranging from 2% to 4%. The thinner is the layer, and the larger is the error. The absolute thickness
variability on the surface of the wafer is kept constant but the relative thickness variability increases
with the sacrificial oxidation. We conclude that the quality of the wafer is essential, in terms of
thickness variation, doping control and interfaces quality. We used a Deal-Grove oxidation model,
corrected for thin oxide growth (See Section 3.2.2).
SiO 2
Buried oxide
Oxidation time, t [min]
Initial SOI thickness: 96nm
Buried oxide
SiO 2
0 20 40 60 80 100 120 140 160 180 200
Oxidation time, t [min]
(1)
(2)

Appendix B 145
APPENDIX B: LIST OF PUBLICATIONS
Contributions on single electronics and silicon nanowires
[1] V. Pott, K. E. Moselund, D. Bouvet and A. M. Ionescu, ’’Gate-all-around and Ω-gate
MOSFET on bulk silicon’’, Poster presentation at the 7 th International Workshop on Future
Information Processing Technologies, Dresden DE, 2007.
[2] A. M. Ionescu, K. Boucart, K. E. Moselund, V. Pott and D. Tsamados, ’’Small slope micro/
nano-electronic switches’’, Invited talk at CAS conference, Sinaia RO, 2007.
[3] K. E. Moselund, P. Dobrosz, S. Olsen, V. Pott, A. O’Neill, L. De Michielis, D. Tsamados, D.
Bouvet, A. O’Neill and A. M. Ionescu, ’’Bended gate-all-around nanowire MOSFET: a
device with enhanced carrier mobility due to oxidation-induced tensile stress’’, Technical
Digest of IEDM, Washington DC, 2007.
[4] K. E. Moselund, V. Pott, D. Bouvet and A. M. Ionescu, ’’Abrupt current switching due to
impact ionization effects in Ω-MOSFET on low doped bulk silicon’’, Proceedings of
ESSDERC, pp. 287-290, Munich DE, 2007.
[5] V. Pott, A. Heeren, K. E. Moselund, M. Fleischer, D. Kern and A. M. Ionescu, ’’Gate-allaround
silicon nanowires for hybrid CMOS / Single Electron Transistor Applications - in the
framework of the SINANO European Network of Excellence’’, Poster presentation at the
INC3 European Nano Day, Brussels BE, 2007.
[6] K. E. Moselund, D. Bouvet, L. Tschuor, V. Pott, P. Dainesi, C. Eggimann, N. Le Thomas, R.
Houdré and A. M. Ionescu, ’’Cointegration of Gate-All-Around MOSFETs and local siliconon-insulator
optical waveguides on bulk silicon’’, IEEE Transactions on Nanotechnology, vol.
6 (1), pp. 118-125, 2007.
[7] V. Pott, D. Bouvet, K. E. Moselund and A. M. Ionescu, ’’Carrier mobility in ultra-scaled gateall-around
silicon nanowires’’, International Conference on Nano Science and Nano
Technology (GJ-NST), Gwangju KO, 2006.
[8] K. E. Moselund, D. Bouvet, L. Tschuor, V. Pott, P. Dainesi and A. M. Ionescu, ’’Local volume
inversion and corner effects in triangular gate-all-around MOSFETs’’, Proceedings of
ESSDERC, pp. 359-362, Montreux CH, 2006.
[9] V. Pott, D. Bouvet, J. Boucart, L. Tschuor, K. E. Moselund and A. M. Ionescu, ’’Low
temperature single electron characteristics in gate-all-around MOSFETs’’, Proceedings of
ESSDERC, pp. 427-430, Montreux CH, 2006.
[10] V. Pott, J. Boucart, D. Bouvet, K. E. Moselund and A. M. Ionescu, ’’Coulomb blockade in
gate-all-around silicon nanowire MOSFETs’’, Proceedings of IEEE silicon nanoelectronics
workshop, pp. 25-26, Honolulu HI, 2006.
[11] K. E. Moselund, L. Tschuor, D. Bouvet, V. Pott, P. Dainesi, C. Eggimann, N. Le Thomas, R.
Houdré and A. M. Ionescu, ’’Co-integration of gate-all-around MOSFETs and local silicon-on
insulator optical waveguides on bulk silicon for GHz on-chip optical signaling’’, Proceedings
of IEEE silicon nanoelectronics workshop, pp. 31-32, Honolulu HI, 2006.
[12] V. Pott and A. M. Ionescu, ’’Conduction in ultra-thin SOI nanowires prototyped by FIB
milling’’, Microelectronic Engineering, vol. 83, pp. 1718-1720, 2006.
[13] V. Pott, D. Bouvet, K. E. Moselund and A. M. Ionescu, ’’Gate-all-around MOSFETs: true
fabrication and characteristics’’, Invited talk at the SINANO workshop on silicon nanodevices,
Aachen DE, 2006.
[14] S. Ecoffey, V. Pott, S. Mahapatra, D. Bouvet and A. M. Ionescu, ’’Hybrid Nanowire-MOS
circuit architectures: from basic physics to digital and analog applications’’, 6 th Nanophysics,
Hanoi VN, 2006.

146 Appendix B
[15] V. Pott, ’’La révolution nanoélectronique’’, Revue A 3 Tracé, Informatique Bio-inspirée, pp.
13, 2006.
[16] S. Ecoffey, M. Mazza, V. Pott, D. Bouvet, A. Schmid, Y. Leblebici, M. Declercq and A. M.
Ionescu, ’’A new logic family based on hybrid MOSFET-polysilicon nanowires’’, Technical
Digest of IEDM, pp. 269-272, Washington DC, 2005.
[17] V. Pott and A. M. Ionescu, ’’Conduction in ultra-thin SOI nanowires prototyped by FIB
milling’’, Conference on Micro and Nano Engineering (MNE), 3_p-05, Vienna AT, 2005.
[18] S. Ecoffey, V. Pott, D. Bouvet, M. Mazza, S. Mahapatra, A. Schmid, Y. Leblebici, M.
Declercq and A. M. Ionescu, ’’Nano-wires for room temperature operated hybrid CMOS-
NANO integrated circuits’’, Digest of Technical Papers of ISSCC, pp. 260-262, 2005.
[19] S. Ecoffey, V. Pott, D. Bouvet, Y. Leblebici, M. Declercq and A. M. Ionescu, ’’Fabrication of
polysilicon gated-nanowires and their application for pA precision current measurements’’,
Digest of TRANSDUCERS, vol. 1, pp. 859-862, Seoul KO, 2005.
[20] D. Grogg, C. Santschi, V. Pott, A. M. Ionescu and J. Brugger, ’’Nanostencil-based lithography
for silicon nanowires fabrication’’, Proceedings of Nanoelectronics Days, pp. 33-34, Jülich
DE, 2005.
[21] V. Pott, D. Grogg, J. Brugger and A. M. Ionescu, ’’Silicon nanowires patterning by sidewall
and nano-oxidation processing’’, Proceedings of Nanoelectronics Days, pp. 19-20, Jülich DE,
2005.
[22] S. Ecoffey, S. Mahapatra, V. Pott, D. Bouvet, G. Reimbold and A. M. Ionescu, ’’Low
temperature investigation of electrical conduction in polysilicon: simulation and experiment’’,
European Nano Systems (ENS), Paris FR, 2005.
[23] A. M. Ionescu, S. Mahapatra and V. Pott, ’’Hybrid SETMOS architecture with Coulomb
blockade oscillations and high current drive’’, Electron Device Letters, vol. 25 (6), pp. 411-
413, 2004.
[24] A. M. Ionescu, V. Pott, S. Ecoffey, S. Mahapatra, K. Moselund, P. Dainesi, K. Buchheit and
M. Mazza, ’’Emerging nanoelectronics: multi-functional nanowires’’, Proceedings of CAS,
vol. 1, pp. 3-8, Sinaia RO, 2004.
[25] A. M. Ionescu, K. Buchheit, P. Dainesi, S. Ecoffey, S. Mahapatra and V. Pott, ’’Nanowires: a
realistic approach for future hybrid nanoelectronics?’’, 3th NID Workshop, Athens GR, 2004.
[26] S. Ecoffey, V. Pott, S. Mahapatra, D. Bouvet, P. Fazan and A. M. Ionescu, ’’A hybrid CMOS-
SET co-fabrication platform using nanograin polysilicon wires’’, Conference on Micro and
Nano Engineering (MNE), pp. 148-149, Rotterdam NL, 2004.
[27] S. Mahapatra, V. Pott and A. M. Ionescu, ’’Few electron Negative Differential Resistance
(NDR) devices’’, Proceedings of CAS, vol 1, pp. 51-54, Sinaia RO, 2003.
[28] S. Mahapatra, V. Pott and A. M. Ionescu, ’’SETMOS-a high current Coulomb blockade
oscillation device’’, Proceedings of ESSDERC, pp. 183-186, Estoril PT, 2003.
[29] S. Mahapatra, V. Pott, S. Ecoffey, A. Schmid, C. Wasshuber, J. W. Tringe, Y. Leblebici, M.
Declercq, K. Banerjee and A. M. Ionescu, ’’SETMOS: a novel true hybrid SET-CMOS high
current Coulomb blockade oscillation cell for future nano-scale analog ICs’’, Technical
Digest of IEDM, pp. 29.7.1 - 29.7.4, Washington DC, 2003.

Appendix B 147
Contributions on other scientific activities
[30] M. Fernández-Bolaños, N. Abelé, V. Pott, D. Bouvet, G. A. Racine, J. M. Quiero and A. M.
Ionescu, ’’Polyimide sacrificial layer for SOI SG-MOSFET pressure sensor’’,
[31]
Microelectronic Engineering, vol. 83, pp. 1185-1188, 2006.
N. Abelé, V. Pott, K. Boucart, F. Casset, K. Séguéni, P. Ancey and A. M. Ionescu,
’’Comparison of RSG-MOSFET and capacitive MEMS resonator detection’’, Electronics
Letters, vol. 41 (5), pp. 242-244, 2005.
[32] N. Abelé, V. Pott, K. Boucart, F. Casset, K. Séguéni, P. Ancey and A.M. Ionescu, ’’Electro-
Mechanical modeling of MEMS resonators with MOSFET detection’’, MSM Nanotech, vol.
3, pp. 553-556, 2005.
[33] M. Fernández-Bolaños, N. Abelé, D. Bouvet, V. Pott, G. Racine, J. Quero and A. M. Ionescu,
’’Polyimide sacrificial layer process for SOI SG-MOSFET pressure sensor’’,Conference on
Micro and Nano Engineering (MNE), 2A-02, Vienna AT, 2005.
[34] R. Fritschi, N. Abelé, V. Pott, C. Hibert, P. Flückiger, P. Ancey and A. M. Ionescu, ’’RF
MEMS switches for mobile communications: from metal-metal to suspended-gate MOS
device architectures’’, European Microwave Week (EuMW), Paris la Défense FR, 2005.
[35] P. A. Besse, G. Boero, M. Demierre, V. Pott and R. S. Popovic, ’’Detection of a single
magnetic microbead using a miniaturized silicon Hall sensor’’, Applied Physics Letters, vol.
80, pp. 4199, 2002.
[36] A. M. Ionescu, V. Pott, R. Fritschi, K. Banerjee, M. Declercq, P. Renaud, C. Hibert, P.
Fluckiger and G.-A. Racine, ’’Modeling and design of a low-voltage SOI suspended-gate
MOSFET (SG-MOSFET) with a metal-over-gate architecture’’, Proceedings of ISQED, pp.
496-501, San Jose CA, 2002.
[37] V. Pott, A. M. Ionescu, R. Fritschi, C. Hibert, P. Fluckiger, M. Declercq, P. Renaud, A. Rusu,
D. Dobrescu and L. Dobrescu, ’’The suspended-gate MOSFET (SG-MOSFET): a modeling
outlook for the design of RF MEMS switches and tunable capacitors’’, Proceedings of CAS,
vol 1, pp. 137-140, Sinaia RO, 2001.
Patents
[38] A. M. Ionescu, P. Fluckiger, C. Hibert, R. Fritschi and V. Pott, ’’Process for manufacturing
MEMS’’, Patent Application: US 20050227428 A1, 2005.
[39] K. E. Moselund, A. M. Ionescu, V. Pott and M. Kayal, ’’New capacitor-less memory and
abrupt switch based on hysteresis characteristics in punch-through impact ionization MOS
transistor (PI-MOS)’’, US 60968651 Patent Pending, 2007.

EDUCATION
APPENDIX C: CURRICULUM VITAE
Vincent POTT
Nanotechnology and Nanoelectronics Engineer
La Crettaz 29
1967 Bramois
SWITZERLAND
E-mail:
Born:
Martial status:
Ph.D. student. Thesis title: May 2002 - Jan. 2008
Gate-all-around silicon nanowires for hybrid Single
Electron Transistor / CMOS applications
Advisor: Prof. Adrian M. Ionescu
Ecole Polytechnique Fédérale de Lausanne (EPFL)
Lausanne, Switzerland
Master Degree (M.Sc.) in Micro-engineering Oct. 1997 - Apr. 2002
Specialization in Microelectronics and Microsystems
Ecole Polytechnique Fédérale de Lausanne (EPFL)
Lausanne, Switzerland
SCIENTIFIC ACHIEVEMENT
Vincent.Pott@a3.epfl.ch
8 th July 1978
Single
Award: Omega Foundation Award for the best diploma in
Microelectronics (April 2002)
Publications: Author and co-author of about 40 scientific publications in
various Conferences (IEDM, ISSCC, ESSDERC, Transducers)
and Journals (Applied Physics Letters, IEEE-TED).
Patents: Co-author of 2 patents.
Place of birth:
Place of origin:
Citizenship:
Sion CH
Mollens CH
Switzerland
Cleanroom: Fully independent work for more than 5 years in a Class 100
cleanroom (http://cmi.epfl.ch).
Physics: Quantum nanoelectronic physics, modelling and technology.
Teaching: Work with undergraduate students (basic electronics, projects,
cleanroom training).

INDUSTRIAL EXPERIENCES
Assembly assistant in a watchmaking compagny 1997 - 1998
ETA SA Fabrique d’Ebauches
Sion, CH
Micro-mechanical and construction training 1999
Ecole Technique des Métiers (ETML)
Lausanne, CH
Cleanroom assistant, LIGA processing 2000
Mimotec SA
Sion, CH
Watch quality control and statistics 2001
Montres Patek-Philippe SA
Genève, CH
LANGUAGE SKILLS
French : Mother tongue
English : Very good in reading, writing and speaking
German : Good understanding, basic of writing
COMPUTER SKILLS
Environment : Windows, Unix
Office : MS-Office, Adobe FrameMaker, Dreamweaver (HTML)
Professional : SolidWorks, Mathematica, L-Edit, Synopsys TCAD tools
PERSONAL INTERESTS
Travelling : Many travels in Europe and Asia
Arts : Interests for general arts, culture and history
Music : Classical, opera
MEMBERSHIPS
IEEE : (S’04, M’07) Institute of Electrical and Electronics
Engineers.
EDS : Member of the Electron Devices Society