Solutions for Mixed-Signal SoC Implementation - Cadence Design ...

Digital timing verification
The verification of digital timing paths inside mixed-signal blocks is problematic in traditional netlist-driven flows.
Typically, digital implementation tools extract path parasitics only to the analog IP block’s instance pin, and any
loading inside the block is modeled by a .lib file (Figure 7, left). Generating that .lib file amounts to a generally
painful experience for analog designers.
A better approach provided by the Encounter Digital Implementation system involves extracting full-path parasitics
all the way to the digital instance pin (Figure 7, right). The tool models the loading of the digital path inside a
mixed-signal block as a distributed RC network. Internal loading is thus appended to the extracted path, and
static timing analysis can verify the complete path with no need to generate a .lib file.
Digital
I1 I2
Path parasitics
extracted to
AMS instance pin
Digital cell library instances
AMS AMS Partition .lib
Towards a new mixed-signal implementation flow
Digital
I1
Extract full path
parasitics to digital
instance pin
Figure 7: Extracting full-path parasitics allows timing closure on
mixed-signal blocks without requiring generation of a .lib file.
Solutions for Mixed-Signal SoC Implementation
I2
AMS Partition
The schematic-driven and netlist-driven flows are block-based approaches that involve the import of one type of
block into a larger analog or digital environment. The emerging mixed-signal flow represents a much more integrated
methodology. While the new flow retains separate analog and digital design teams and tools, responsibility for the
overall design, verification and chip tapeout is shared.
One big advance with this new approach is that analog and digital blocks can be designed concurrently. Floorplanning
can be truly mixed-signal, with flexibility to assign or optimize pins. With flexible pinouts, designers do not need to
send analog or digital blocks back for rework if they find that fixed pinouts don’t work in a floorplan. Results can include
earlier floorplanning, smaller area, less routing congestion, earlier chip finishing, and faster overall turn-around times.
Figure 8 shows an advanced mixed-signal implementation flow. Notice how the top-level floorplan becomes a joint
exercise between analog and digital design groups. These teams concurrently optimize the floorplan, changing
pinouts and locations and routing nets as needed, until they can both sign off on the floorplan. Each team must be
aware of the constraints on the other side.
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