Solutions for Mixed-Signal SoC Implementation - Cadence Design ...

Floorplanning and prototyping precede detailed digital implementation. In the Encounter Digital Implementation
system, chip prototyping provides a very rapid full-chip representation that allows users to improve their floorplan
for congestion and timing. While not “DRC clean,” the prototype provides a high level of confidence that the
design and floorplan won’t cause top-level implementation and timing closure problems later.
After analog blocks are imported, and digital blocks are imported or created, top-level implementation takes
place in the digital environment. Analog blocks may have specific area or aspect ratio requirements that must be
met. Chip assembly and analysis mostly take place in the digital environment, although some of the verification,
extraction and analysis may take place on the analog side. SoC signoff requires static timing, signal integrity,
and IR drop analyses, and the integrator must ensure that any additions or fixes don’t negatively impact analog/
digital interfaces.
The Cadence Virtuoso and Encounter platforms support a single design database on OpenAccess, greatly simplifying
the transfer of analog blocks to and from the Virtuoso environment. Physical design data, hierarchical netlists,
and mixed-signal routing constraints can all be saved with OpenAccess.
Encounter mixed signal GXL option
In the Cadence flow, the Encounter Mixed Signal GXL option provides enhanced support for netlist-driven mixedsignal
flows. With the Mixed Signal GXL option, digital designers using Encounter have full visibility into Pcell
layouts for analog IP blocks (Figure 6). Guard rings, however, can be frozen when editing. Additionally, a mixedsignal
routing capability manages analog constraints such as shielding, matching, differential pairs, and bus routing
while still providing high-speed digital routing.
Substrate analysis
Implement custom design, add
guard rings and pCells
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Virtuoso Encounter
Open Access
Load design into digital environment,
guard rings edit locked, pCells fully
visible, ECO sees all non-P&R objects
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Sea-of-Cells
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Figure 6: OpenAccess eases the integration of analog IP into mostly digital SoC designs.
Solutions for Mixed-Signal SoC Implementation
Mixed-signal designs raise the risk of chip malfunction due to coupling through the substrate. One way or another,
designers must predict and minimize substrate noise. Full-chip substrate analysis is an emerging capability that
can help designers determine where guard rings are required, and whether spacing is sufficient to avoid substrate
noise. The analysis should identify digital noise sources caused by simultaneous switching, model noise transmission
through the substrate, and report the impact of digital noise on sensitive analog components.
Without substrate noise analysis, a conservative approach that makes heavy use of guard rings or employs a triplewell
silicon process may be required, leading to additional area, cost, and the possibility of additional coupling.
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