Solutions for Mixed-Signal SoC Implementation - Cadence Design ...

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D A D Digital SoC A D D A A D A D D D Analog IP A D Digital Logic Figure 1: Digital logic often resides inside analog IP that is integrated into SoCs. SoCs must interact with the outside world through displays, antennas, sensors, or other means, and this functionality is increasingly integrated on-chip. Due to rapidly expanding capacity, a single IP block may represent a complex mixed-signal function that may have been an entire chip in a previous process generation. Since analog circuitry doesn’t scale as well as digital, analog/mixed-signal circuitry may take up half the area of an SoC. Today’s physical implementation methodologies are generally either “netlist-driven” flows from a digital cockpit or “schematic-driven” flows from an analog cockpit. In both cases, these flows were developed to deal with relatively simple integration challenges. While these methodologies will remain important, SoC designers need a new approach as the amount of complex mixed-signal content grows, and analog and digital circuits become more functionally coupled. Under this new approach, analog and digital blocks will be designed concurrently, and will have flexible pin assignments so they can be placed within a true mixed-signal floorplan. While analog and digital designers will still retain their own familiar design environments, a common database representation will simplify the integration of analog, digital and mixed-signal blocks. Responsibility for chip assembly and tapeout will be shared. In short, there will be no hard separation between “analog” and “digital” design. A Gap Between Divergent Flows Challenges Mixed-Signal Implementation Solutions for Mixed-Signal SoC Implementation Mixed-signal SoC implementation is a complicated task because it involves two very different design and verification flows. In a traditional setting, analog and digital blocks are designed by separate teams using entirely different tools, with little communication between the teams and little understanding of the environment and the challenges on the other side. The analog design flow is schematic-driven, with lots of physical hierarchy. While today’s analog/custom design environments offer some semi-automated features, analog design is traditionally manual and interactive. The analog flow is largely transistor-based, requiring a level of detail that is mostly hidden on the digital side. The analog flow typically involves drawing schematics, simulating functionality, drawing or editing polygons to implement the design, and then executing layout-versus-schematic (LVS) checking to make sure the layout matches the schematics. In more advanced systems such as the Cadence ® Virtuoso ® Layout Suite, the analog flow often includes the use of parameterized cells (Pcells) and the selective use of automated placement and routing. The analog flow makes heavy use of physical and electrical constraints. For example, analog layouts may have constraints related to shielding, differential pairs, matched lengths, and symmetry. Digital floorplanning, placement and routing systems need to understand these constraints. The digital design flow, in contrast, is netlist-driven and heavily automated, and uses RTL synthesis—or even SystemC synthesis—to generate gate-level logic. Aimed at designing ICs with tens or hundreds of millions of gates, the flow employs cell libraries that hide transistor-level details from the designer. Floorplanning, placement, and routing are timing-driven and automated. www.cadence.com 2 D
When analog blocks are imported into a largely digital SoC design, the blocks are typically black boxes that give digital designers no visibility into the layouts. The analog blocks typically have fixed guard rings and pinouts. The hardened IP leads to a lack of flexibility in floorplanning, resulting in a less than optimal floorplan. The SoC integrator has to assume that the analog designer adequately verified the block. It is possible, for instance, to get all the way to design rule checking and find out that a control signal is inverted because the block was never timed or simulated. Even if all the digital and analog blocks are thoroughly verified at the block level, chip-level verification across analog and digital interfaces is still very challenging. Analog designers who import digital blocks face a number of challenges as well. Digital blocks may have pinouts that are suboptimal in an analog/mixed-signal floorplan. Digital circuitry can cause noise and signal integrity problems, requiring analog designers to use adequate shielding. Large amounts of simultaneously switching digital circuitry can cause noise that can get into the substrate and be transmitted throughout the design, resulting in oscillations and voltage noise in sensitive analog circuitry. Noise can also be transmitted around a chip via the power routes, the package and the substrate. The traditional mixed-signal implementation flow results in frequent engineering change orders (ECOs). Analog and digital design teams may have to go back and forth to iteratively change pinouts, floorplans, physical layouts, and other design attributes to satisfy the constraints and performance demands of both analog and digital circuitry. Late-stage ECOs may even force a redo of chip assembly and chip finishing. Steps Towards an Integrated Solution Analog and digital design requirements, methodologies and skill sets are fundamentally different, and design teams are used to their respective tool environments. A single GUI/interface that handles both analog and digital design may never be practical, because it forces one, or both, teams away from their proven environment. What is possible and needed, however, is a planning-to-signoff methodology and solution for the design, analysis and verification of mixed-signal SoCs that enables easy and efficient interaction between the analog and digital teams. The solution needs to support SoC integration with large analog, digital and mixed-signal IP blocks. From a physical implementation perspective, the solution needs to handle system-level design, block-level design, chip assembly, physical verification, and system verification. Figure 2 shows some of the components of a mixedsignal implementation system. System-Level Design Block-Level Design Chip Assembly Physical Verification System Verification Functional Design and Verification RTL Design and Verification Synthesis and Verification Place and Route Chip Planning DRC, LVS, RCX Chip Assembly Design and Analysis Circuit Simulation Custom Layout Full Chip Physical Verification, Extraction, and Analysis Full Chip System-Level Verification Analog, Digital, RF Figure 2: Components of a mixed-signal design solution Solutions for Mixed-Signal SoC Implementation www.cadence.com 3
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