Solutions for Mixed-Signal SoC Implementation - Cadence Design ...

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Digital SoC
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Analog IP
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Digital Logic
Figure 1: Digital logic often resides inside analog IP that is integrated into SoCs.
SoCs must interact with the outside world through displays, antennas, sensors, or other means, and this functionality
is increasingly integrated on-chip. Due to rapidly expanding capacity, a single IP block may represent a complex
mixed-signal function that may have been an entire chip in a previous process generation. Since analog circuitry
doesn’t scale as well as digital, analog/mixed-signal circuitry may take up half the area of an SoC.
Today’s physical implementation methodologies are generally either “netlist-driven” flows from a digital cockpit
or “schematic-driven” flows from an analog cockpit. In both cases, these flows were developed to deal with
relatively simple integration challenges. While these methodologies will remain important, SoC designers need a
new approach as the amount of complex mixed-signal content grows, and analog and digital circuits become more
functionally coupled.
Under this new approach, analog and digital blocks will be designed concurrently, and will have flexible pin assignments
so they can be placed within a true mixed-signal floorplan. While analog and digital designers will still retain
their own familiar design environments, a common database representation will simplify the integration of analog,
digital and mixed-signal blocks. Responsibility for chip assembly and tapeout will be shared. In short, there will be
no hard separation between “analog” and “digital” design.
A Gap Between Divergent Flows Challenges Mixed-Signal Implementation
Solutions for Mixed-Signal SoC Implementation
Mixed-signal SoC implementation is a complicated task because it involves two very different design and verification
flows. In a traditional setting, analog and digital blocks are designed by separate teams using entirely
different tools, with little communication between the teams and little understanding of the environment and the
challenges on the other side.
The analog design flow is schematic-driven, with lots of physical hierarchy. While today’s analog/custom design
environments offer some semi-automated features, analog design is traditionally manual and interactive. The
analog flow is largely transistor-based, requiring a level of detail that is mostly hidden on the digital side.
The analog flow typically involves drawing schematics, simulating functionality, drawing or editing polygons to
implement the design, and then executing layout-versus-schematic (LVS) checking to make sure the layout matches
the schematics. In more advanced systems such as the Cadence ® Virtuoso ® Layout Suite, the analog flow often
includes the use of parameterized cells (Pcells) and the selective use of automated placement and routing.
The analog flow makes heavy use of physical and electrical constraints. For example, analog layouts may have
constraints related to shielding, differential pairs, matched lengths, and symmetry. Digital floorplanning, placement
and routing systems need to understand these constraints.
The digital design flow, in contrast, is netlist-driven and heavily automated, and uses RTL synthesis—or even
SystemC synthesis—to generate gate-level logic. Aimed at designing ICs with tens or hundreds of millions of gates,
the flow employs cell libraries that hide transistor-level details from the designer. Floorplanning, placement, and
routing are timing-driven and automated.
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