Solutions for Mixed-Signal SoC Implementation - Cadence Design ...
Solutions for Mixed-Signal SoC Implementation - Cadence Design ...
Solutions for Mixed-Signal SoC Implementation - Cadence Design ...
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Conclusion<br />
<strong>Solutions</strong> <strong>for</strong> <strong>Mixed</strong>-<strong>Signal</strong> <strong>SoC</strong> <strong>Implementation</strong><br />
As lower process nodes allow bigger and denser chips—enabling designers to pack more and more functionality<br />
onto a single chip—<strong>SoC</strong> implementation is becoming increasingly difficult. Additionally, today’s <strong>SoC</strong> designs<br />
include more analog blocks, and a growing number of blocks have both analog and digital circuitry and are thus<br />
truly mixed-signal.<br />
Historically, mixed-signal implementation methodologies involved the import of hardened analog blocks onto a<br />
digital chip, or small amounts of digital logic into analog blocks or ICs. Analog and digital designers often worked<br />
in isolation with little understanding of the challenges and constraints on the other side. The net result was an<br />
ECO-driven flow in which pinouts, floorplans, placement and routing, and tapeouts went through a number of<br />
iterations to produce a working chip.<br />
Still, the existing schematic-driven and netlist-driven implementation flows remain important, and they can be<br />
optimized and improved with a well thought-out methodology that includes a top-level floorplan, analog/digital<br />
block implementation, top-level implementation, and chip assembly and analysis. A common database representation<br />
can greatly ease these flows. Features such as mixed-signal routing, visibility into analog blocks, and<br />
extraction of digital timing paths also aid designers in overcoming <strong>SoC</strong> challenges.<br />
The solution that’s emerging now is an integrated mixed-signal implementation methodology in which chip<br />
planning, design, implementation, physical verification, and tapeout are shared responsibilities between analog<br />
and digital teams. Analog and digital blocks can be concurrently designed, and floorplanning can be a shared<br />
exercise. This type of flow makes use of the OpenAccess database to provide quick access to all design data by<br />
both analog and digital teams. It also leverages the strengths of existing analog and digital design environments,<br />
using capabilities from each where appropriate.<br />
The new mixed-signal flow supported by <strong>Cadence</strong> will help both analog and digital designers more efficiently<br />
implement complex mixed-signal designs.<br />
<strong>Cadence</strong> is trans<strong>for</strong>ming the global electronics industry through a vision called EDA360.<br />
With an application-driven approach to design, our software, hardware, IP, and services help<br />
customers realize silicon, <strong>SoC</strong>s, and complete systems efficiently and profitably. www.cadence.com<br />
©2011 <strong>Cadence</strong> <strong>Design</strong> Systems, Inc. All rights reserved. <strong>Cadence</strong> and the <strong>Cadence</strong> logo are registered trademarks of <strong>Cadence</strong> <strong>Design</strong> Systems, Inc.,<br />
All rights reserved. <strong>Cadence</strong> and the <strong>Cadence</strong> logo are registered trademarks of <strong>Cadence</strong> <strong>Design</strong> Systems, Inc., All rights reserved. <strong>Cadence</strong> and the<br />
<strong>Cadence</strong> logo are registered trademarks of <strong>Cadence</strong> <strong>Design</strong> Systems, Inc. 21248 12/11 RG/DM/PDF