Solutions for Mixed-Signal SoC Implementation - Cadence Design ...

Solutions for Mixed-Signal SoC
Implementation
By Peter McCrorie, Randolph Fish, and Richard Goering Cadence Design Systems Inc.
Companies designing mixed-signal SoCs are running into several challenges caused by today’s
disjointed analog and digital design flows. This paper discusses current implementation flows
and introduces an emerging integrated mixed-signal implementation methodology in which chip
planning, design, implementation, physical verification, and tapeout are shared responsibilities
between analog and digital teams. Cadence supports this new mixed-signal flow that will help
analog and digital designers more efficiently implement complex mixed-signal designs.
Contents
Introduction .................................1
The Hierarchical Nature of
Today’s Mixed-Signal Designs .......1
A Gap Between
Divergent Flows Challenges
Mixed-Signal Implementation .......2
Steps Towards
an Integrated Solution .................3
Mixed-Signal
Implementation Flows ..................4
Conclusion ................................. 10
Introduction
Since virtually all systems on chip (SoCs) contain some analog circuitry, many
SoC design engineers have some familiarity with mixed-signal implementation.
Nevertheless, a new set of challenges is emerging as the amount of analog
circuitry increases, and the use of digital control logic inside analog blocks
grows. These developments are blurring the boundaries between “analog”
and “digital.” Consequently, mixed-signal SoC implementation today requires
far more than the traditional practice of importing a few analog “black boxes”
that were designed independently from the digital circuitry.
This paper focuses on advanced mixed-signal SoC implementation flows and
solutions. It describes some of the common challenges that result from today’s
disjointed analog and digital design flows. It then discusses current implementation
flows, presents a new flow that allows concurrent analog and digital
design, and notes solutions that support all these flows. A previous Cadence
white paper discussed mixed-signal design challenges, and a subsequent paper
will discuss the increasingly important topic of mixed-signal verification.
The Hierarchical Nature of Today’s Mixed-Signal Designs
Mixed-signal design has become hierarchical, with analog blocks residing
inside digital functions that control analog signals. With the trend towards
digitally assisted analog, devices such as phase-lock loops (PLLs) and analog/
digital converters (ADCs) contain increasing amounts of digital control logic
as well as digital signal processing. Conversely, digital blocks may incorporate
high-speed I/Os and power domain management circuitry with substantial
analog content.

D
A
D
Digital SoC
A
D
D
A
A
D
A
D
D
D
Analog IP
A
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Digital Logic
Figure 1: Digital logic often resides inside analog IP that is integrated into SoCs.
SoCs must interact with the outside world through displays, antennas, sensors, or other means, and this functionality
is increasingly integrated on-chip. Due to rapidly expanding capacity, a single IP block may represent a complex
mixed-signal function that may have been an entire chip in a previous process generation. Since analog circuitry
doesn’t scale as well as digital, analog/mixed-signal circuitry may take up half the area of an SoC.
Today’s physical implementation methodologies are generally either “netlist-driven” flows from a digital cockpit
or “schematic-driven” flows from an analog cockpit. In both cases, these flows were developed to deal with
relatively simple integration challenges. While these methodologies will remain important, SoC designers need a
new approach as the amount of complex mixed-signal content grows, and analog and digital circuits become more
functionally coupled.
Under this new approach, analog and digital blocks will be designed concurrently, and will have flexible pin assignments
so they can be placed within a true mixed-signal floorplan. While analog and digital designers will still retain
their own familiar design environments, a common database representation will simplify the integration of analog,
digital and mixed-signal blocks. Responsibility for chip assembly and tapeout will be shared. In short, there will be
no hard separation between “analog” and “digital” design.
A Gap Between Divergent Flows Challenges Mixed-Signal Implementation
Solutions for Mixed-Signal SoC Implementation
Mixed-signal SoC implementation is a complicated task because it involves two very different design and verification
flows. In a traditional setting, analog and digital blocks are designed by separate teams using entirely
different tools, with little communication between the teams and little understanding of the environment and the
challenges on the other side.
The analog design flow is schematic-driven, with lots of physical hierarchy. While today’s analog/custom design
environments offer some semi-automated features, analog design is traditionally manual and interactive. The
analog flow is largely transistor-based, requiring a level of detail that is mostly hidden on the digital side.
The analog flow typically involves drawing schematics, simulating functionality, drawing or editing polygons to
implement the design, and then executing layout-versus-schematic (LVS) checking to make sure the layout matches
the schematics. In more advanced systems such as the Cadence ® Virtuoso ® Layout Suite, the analog flow often
includes the use of parameterized cells (Pcells) and the selective use of automated placement and routing.
The analog flow makes heavy use of physical and electrical constraints. For example, analog layouts may have
constraints related to shielding, differential pairs, matched lengths, and symmetry. Digital floorplanning, placement
and routing systems need to understand these constraints.
The digital design flow, in contrast, is netlist-driven and heavily automated, and uses RTL synthesis—or even
SystemC synthesis—to generate gate-level logic. Aimed at designing ICs with tens or hundreds of millions of gates,
the flow employs cell libraries that hide transistor-level details from the designer. Floorplanning, placement, and
routing are timing-driven and automated.
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When analog blocks are imported into a largely digital SoC design, the blocks are typically black boxes that give
digital designers no visibility into the layouts. The analog blocks typically have fixed guard rings and pinouts. The
hardened IP leads to a lack of flexibility in floorplanning, resulting in a less than optimal floorplan.
The SoC integrator has to assume that the analog designer adequately verified the block. It is possible, for instance,
to get all the way to design rule checking and find out that a control signal is inverted because the block was never
timed or simulated. Even if all the digital and analog blocks are thoroughly verified at the block level, chip-level
verification across analog and digital interfaces is still very challenging.
Analog designers who import digital blocks face a number of challenges as well. Digital blocks may have pinouts
that are suboptimal in an analog/mixed-signal floorplan. Digital circuitry can cause noise and signal integrity
problems, requiring analog designers to use adequate shielding. Large amounts of simultaneously switching digital
circuitry can cause noise that can get into the substrate and be transmitted throughout the design, resulting in
oscillations and voltage noise in sensitive analog circuitry. Noise can also be transmitted around a chip via the
power routes, the package and the substrate.
The traditional mixed-signal implementation flow results in frequent engineering change orders (ECOs). Analog
and digital design teams may have to go back and forth to iteratively change pinouts, floorplans, physical layouts,
and other design attributes to satisfy the constraints and performance demands of both analog and digital circuitry.
Late-stage ECOs may even force a redo of chip assembly and chip finishing.
Steps Towards an Integrated Solution
Analog and digital design requirements, methodologies and skill sets are fundamentally different, and design
teams are used to their respective tool environments. A single GUI/interface that handles both analog and digital
design may never be practical, because it forces one, or both, teams away from their proven environment. What
is possible and needed, however, is a planning-to-signoff methodology and solution for the design, analysis and
verification of mixed-signal SoCs that enables easy and efficient interaction between the analog and digital teams.
The solution needs to support SoC integration with large analog, digital and mixed-signal IP blocks.
From a physical implementation perspective, the solution needs to handle system-level design, block-level design,
chip assembly, physical verification, and system verification. Figure 2 shows some of the components of a mixedsignal
implementation system.
System-Level Design
Block-Level Design
Chip Assembly
Physical Verification
System Verification
Functional Design and Verification
RTL Design and
Verification
Synthesis and
Verification
Place and
Route
Chip Planning
DRC, LVS, RCX
Chip Assembly
Design and
Analysis
Circuit
Simulation
Custom Layout
Full Chip Physical Verification,
Extraction, and Analysis
Full Chip System-Level Verification
Analog, Digital, RF
Figure 2: Components of a mixed-signal design solution
Solutions for Mixed-Signal SoC Implementation
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Some desirable characteristics of a mixed-signal implementation solution include the following:
• The ability of digital designers to “push into” analog blocks and view their layouts
• The ability for analog designers to implement digital functionality within their hierarchical floorplan
• A common design database, such as OpenAccess, instead of a more limited layout representation using
LEF/DEF or GDSII file transfers of analog or digital blocks
• A chip planning capability such as the Cadence Chip Planning System that allows users to select analog,
digital and mixed/signal IP and obtain early estimates of size, power consumption, performance and cost
• A common design constraint definition for digital and analog, such that constraints developed on either side
can be understood on the other side
• A mixed-signal router that can understand analog constraints such as symmetry and differential pair routing
• Routing solutions that can optimize the routes for yield (DFY) objectives
• A capability to extract digital paths in analog blocks for static timing analysis, so that analog designers don’t
have to manually build complex .lib files
• The ability for analog designers to prevent editing of their sensitive, finely tuned circuits by SoC integrators.
• A hierarchical design approach that can manage analog and digital design styles
In addition to meeting specific demands related to mixed-signal integration, a mixed-signal design flow must
provide the performance and capacity needed for today’s extremely large and dense SoC designs, and must
meet all the design for manufacturability (DFM) requirements of advanced process nodes. It must also support
low-power design for both digital and analog IP.
Mixed-Signal Implementation Flows
As previously noted, there are two types of established mixed-signal implementation flows:
• Schematic-driven flows, in which a custom design environment such as the Virtuoso Layout Suite platform
handles the floorplanning, chip assembly and block integration. Digital blocks are custom designed or imported
from a digital design environment such as Cadence Encounter ® Digital Implementation system.
• Netlist-driven (Verilog/VHDL) flows, in which the floorplanning, chip assembly and block integration are handled
in a digital design system. Hardened analog IP blocks are imported from an analog/custom design environment
such as the Virtuoso Layout Suite.
Today’s growing and ever-changing mixed-signal requirements demand that these established flows evolve into
flows where floorplanning and chip assembly are shared between the analog and digital design teams, and where
both analog and digital blocks are developed concurrently, requiring extended flexibility in implementation.
The schematic-driven flow
Solutions for Mixed-Signal SoC Implementation
This type of flow is driven by schematic entry and makes extensive use of constraints. Custom designers often
draw schematics for full-chip block-assembly as well as smaller, hierarchical digital blocks, and may use custom
generators for complex datapath and array based modules. For larger digital blocks, an increasing number of
design teams start with Verilog HDL code, making it possible to take advantage of digital synthesis, placement and
routing. The Cadence Virtuoso platform provides a utility that translates a schematic into a Verilog netlist.
A more detailed look at the schematic-driven mixed-signal flow is shown in Fig. 3. Here, the orange coloring
identifies tasks typically done in an analog/custom environment, while blue coloring indicates tasks typically
done in a digital IC design environment.
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Chip Design
(Schematic)
Top-Level Floorplanning
Custom Block
Implementation
Digital Block
Implementation
Top-Level Implementation
Chip Assembly and Analysis
Figure 3: The schematic-driven implementation flow
In the schematic-driven flow, top-level floorplanning for both analog and digital blocks is typically done in a hierarchical
analog environment such as that provided by the Virtuoso platform. This floorplanning takes place before
blocks are implemented. Blocks must be placed to avoid signal integrity problems and to allow sufficient routing
resources. Special care must be taken to properly place sensitive analog blocks that can be impacted by digital
switching noise.
Analog and digital pinout definitions are drawn from the floorplan in a top-down or bottom-up strategy. However,
analog floorplanning is interactive and may be capacity constrained. If there are a large number of pins associated
with a place and route block, a more automated digital floorplanner may be preferred.
After a floorplan is developed, the implementation of individual blocks is handled in the appropriate design
environment. Some blocks may also be pre-designed or purchased IP. The completed analog and digital blocks are
then brought back into the custom design system for top-level implementation and chip assembly. Top-level mixed
signal and chip assembly routing can be achieved using the Virtuoso Space-Based Router. Some analysis, however,
may be done in the digital environment, such as static timing analysis during block creation.
One requirement of this flow is an ability to easily handle late-stage ECOs, including custom ECOs from the
schematic and Verilog netlist changes for the synthesized digital blocks.
Virtuoso digital implementation
Solutions for Mixed-Signal SoC Implementation
To facilitate digital block creation for schematic-driven flows, the Cadence Virtuoso Digital Implementation
tool provides a capacity-limited version of the Encounter Digital Implementation System. This allows analog/
custom designers to quickly develop digital blocks using an automated, timing-driven digital implementation
flow, and bring them back into the Virtuoso platform using GDSII, LEF/DEF or OpenAccess. Virtuoso Digital
Implementation includes RTL synthesis, silicon virtual prototyping, placement, routing, clock tree synthesis,
extraction, and advanced power planning. The solution can be driven by a script, easing digital implementation
for analog designers.
The best way to use Virtuoso Digital Implementation is with OpenAccess, an open industry database developed by
Cadence that provides much faster and more complete file transfers than LEF/DEF. As shown in Figure 4 below, a
top-level schematic is drawn in Virtuoso, and a digital block is passed to Encounter for implementation. It is then
returned to Virtuoso, where chip finishing takes place.
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VIRTUOSO
Netlist-driven flow
Draw Top Level
Chip Finishing
OPEN ACCESS
Design Library Constraints
Synthesis using RTL Compiler
Implementation in Encounter
Placement
Optimization preCTS
Clock Tree Synthesis
Optimization postCTS
Routing
Add Filler cells
Verification
Figure 4: By sharing the OpenAccess database, Virtuoso and Encounter
users can rapidly transfer analog and digital blocks back and forth.
The netlist-driven flow takes place primarily within a timing-driven digital design environment (Figure 5). It typically
uses hardened analog IP designed by an analog design group or third-party provider. The layout for the analog IP
is completed, the pinouts are typically fixed, and guard rings are locked into place using the Virtuoso Layout Suite.
This may take place before any digital design has begun.
Custom IP Block Implementation
Chip Design (Verilog)
Prototyping
Digital Implementation
Top-Level Implementation
Chip Assembly and Analysis
Figure 5: Netlist-driven implementation flow
Solutions for Mixed-Signal SoC Implementation
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ENCOUNTER

Floorplanning and prototyping precede detailed digital implementation. In the Encounter Digital Implementation
system, chip prototyping provides a very rapid full-chip representation that allows users to improve their floorplan
for congestion and timing. While not “DRC clean,” the prototype provides a high level of confidence that the
design and floorplan won’t cause top-level implementation and timing closure problems later.
After analog blocks are imported, and digital blocks are imported or created, top-level implementation takes
place in the digital environment. Analog blocks may have specific area or aspect ratio requirements that must be
met. Chip assembly and analysis mostly take place in the digital environment, although some of the verification,
extraction and analysis may take place on the analog side. SoC signoff requires static timing, signal integrity,
and IR drop analyses, and the integrator must ensure that any additions or fixes don’t negatively impact analog/
digital interfaces.
The Cadence Virtuoso and Encounter platforms support a single design database on OpenAccess, greatly simplifying
the transfer of analog blocks to and from the Virtuoso environment. Physical design data, hierarchical netlists,
and mixed-signal routing constraints can all be saved with OpenAccess.
Encounter mixed signal GXL option
In the Cadence flow, the Encounter Mixed Signal GXL option provides enhanced support for netlist-driven mixedsignal
flows. With the Mixed Signal GXL option, digital designers using Encounter have full visibility into Pcell
layouts for analog IP blocks (Figure 6). Guard rings, however, can be frozen when editing. Additionally, a mixedsignal
routing capability manages analog constraints such as shielding, matching, differential pairs, and bus routing
while still providing high-speed digital routing.
Substrate analysis
Implement custom design, add
guard rings and pCells
D
A
Digital
Sea-of-Cells
P
P
Analog
D
A
Easy, round-trip
data transfers
Virtuoso Encounter
Open Access
Load design into digital environment,
guard rings edit locked, pCells fully
visible, ECO sees all non-P&R objects
D
A
Digital
Sea-of-Cells
P
P
Analog
Figure 6: OpenAccess eases the integration of analog IP into mostly digital SoC designs.
Solutions for Mixed-Signal SoC Implementation
Mixed-signal designs raise the risk of chip malfunction due to coupling through the substrate. One way or another,
designers must predict and minimize substrate noise. Full-chip substrate analysis is an emerging capability that
can help designers determine where guard rings are required, and whether spacing is sufficient to avoid substrate
noise. The analysis should identify digital noise sources caused by simultaneous switching, model noise transmission
through the substrate, and report the impact of digital noise on sensitive analog components.
Without substrate noise analysis, a conservative approach that makes heavy use of guard rings or employs a triplewell
silicon process may be required, leading to additional area, cost, and the possibility of additional coupling.
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Digital timing verification
The verification of digital timing paths inside mixed-signal blocks is problematic in traditional netlist-driven flows.
Typically, digital implementation tools extract path parasitics only to the analog IP block’s instance pin, and any
loading inside the block is modeled by a .lib file (Figure 7, left). Generating that .lib file amounts to a generally
painful experience for analog designers.
A better approach provided by the Encounter Digital Implementation system involves extracting full-path parasitics
all the way to the digital instance pin (Figure 7, right). The tool models the loading of the digital path inside a
mixed-signal block as a distributed RC network. Internal loading is thus appended to the extracted path, and
static timing analysis can verify the complete path with no need to generate a .lib file.
Digital
I1 I2
Path parasitics
extracted to
AMS instance pin
Digital cell library instances
AMS AMS Partition .lib
Towards a new mixed-signal implementation flow
Digital
I1
Extract full path
parasitics to digital
instance pin
Figure 7: Extracting full-path parasitics allows timing closure on
mixed-signal blocks without requiring generation of a .lib file.
Solutions for Mixed-Signal SoC Implementation
I2
AMS Partition
The schematic-driven and netlist-driven flows are block-based approaches that involve the import of one type of
block into a larger analog or digital environment. The emerging mixed-signal flow represents a much more integrated
methodology. While the new flow retains separate analog and digital design teams and tools, responsibility for the
overall design, verification and chip tapeout is shared.
One big advance with this new approach is that analog and digital blocks can be designed concurrently. Floorplanning
can be truly mixed-signal, with flexibility to assign or optimize pins. With flexible pinouts, designers do not need to
send analog or digital blocks back for rework if they find that fixed pinouts don’t work in a floorplan. Results can include
earlier floorplanning, smaller area, less routing congestion, earlier chip finishing, and faster overall turn-around times.
Figure 8 shows an advanced mixed-signal implementation flow. Notice how the top-level floorplan becomes a joint
exercise between analog and digital design groups. These teams concurrently optimize the floorplan, changing
pinouts and locations and routing nets as needed, until they can both sign off on the floorplan. Each team must be
aware of the constraints on the other side.
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Chip Design
(Schematic/Netlist)
Top-Level Floorplanning
Custom Block
Implementation
Digital Block
Implementation
Top-Level Implementation
Chip Assembly and Analysis
Figure 8: Advanced mixed-signal implementation flow
Once the floorplan is completed, custom and digital block implementation then follow in separate analog and
digital environments. Some blocks may also be imported as pre-existing or purchased IP. Top-level implementation,
like floorplanning, becomes a shared exercise between analog and digital teams, with necessary readjustments
made on either side. Chip assembly and analysis are shared as well.
The Cadence environment provides support for an integrated mixed-signal flow. Top-level floorplanning and
prototyping are typically completed in Encounter, which offers automated capabilities. Design partitioning from
floorplanning enables concurrent analog/digital block design and optimization. Digital logic is implemented
in Encounter, and analog blocks are implemented in Virtuoso. Chip assembly and full-chip signoff analysis are
typically completed in Encounter.
The fast data transfers enabled by the shared OpenAccess database make this type of flow possible. Instead of
slow, incomplete LEF/DEF transfers of black boxes, analog and digital designers can quickly view and manipulate
analog and digital blocks. But analog designers can still “lock” features such as guard rings to protect them from
unwanted editing.
Other important characteristics of the advanced mixed-signal flow supported by Cadence technology include:
• The ability for the mixed-signal router to understand analog routing constraints
• The ability to view the complete design in a digital environment
• Improved pin optimization for analog and digital blocks
• Use of manual/interactive and automated hierarchical floorplanning for analog and digital circuitry
• Seamless data transfer between analog and digital designers
• The ability to mix digital and analog circuitry in the same area without hierarchy constraints
• ECOs that can be implemented in either environment
• Digital timing closure that covers all digital logic and paths
• Late-stage ECOs on digital blocks that don’t disrupt chip-finishing details
Solutions for Mixed-Signal SoC Implementation
• Chip assembly routing with support for complex analog requirements as well as high-capacity digital needs
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Conclusion
Solutions for Mixed-Signal SoC Implementation
As lower process nodes allow bigger and denser chips—enabling designers to pack more and more functionality
onto a single chip—SoC implementation is becoming increasingly difficult. Additionally, today’s SoC designs
include more analog blocks, and a growing number of blocks have both analog and digital circuitry and are thus
truly mixed-signal.
Historically, mixed-signal implementation methodologies involved the import of hardened analog blocks onto a
digital chip, or small amounts of digital logic into analog blocks or ICs. Analog and digital designers often worked
in isolation with little understanding of the challenges and constraints on the other side. The net result was an
ECO-driven flow in which pinouts, floorplans, placement and routing, and tapeouts went through a number of
iterations to produce a working chip.
Still, the existing schematic-driven and netlist-driven implementation flows remain important, and they can be
optimized and improved with a well thought-out methodology that includes a top-level floorplan, analog/digital
block implementation, top-level implementation, and chip assembly and analysis. A common database representation
can greatly ease these flows. Features such as mixed-signal routing, visibility into analog blocks, and
extraction of digital timing paths also aid designers in overcoming SoC challenges.
The solution that’s emerging now is an integrated mixed-signal implementation methodology in which chip
planning, design, implementation, physical verification, and tapeout are shared responsibilities between analog
and digital teams. Analog and digital blocks can be concurrently designed, and floorplanning can be a shared
exercise. This type of flow makes use of the OpenAccess database to provide quick access to all design data by
both analog and digital teams. It also leverages the strengths of existing analog and digital design environments,
using capabilities from each where appropriate.
The new mixed-signal flow supported by Cadence will help both analog and digital designers more efficiently
implement complex mixed-signal designs.
Cadence is transforming the global electronics industry through a vision called EDA360.
With an application-driven approach to design, our software, hardware, IP, and services help
customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com
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