6114_SimRFMS_WP2.qxp - Cadence Design Systems

WHITE PAPER
SIMULATING COMPLEX RF/MIXED-SIGNAL DESIGNS USING
VIRTUOSO ULTRASIM FULL-CHIP SIMULATOR

TABLE OF CONTENTS
1 Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Virtuoso UltraSim technology advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Using Virtuoso UltraSim for RF/MS simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Case studies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TABLE OF FIGURES
Figure 1 PLL simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 2 RF PLL simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 3 ADC simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 4 Voltage generator simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 5 Fast envelope following simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

1 ABSTRACT
Recently, the explosive growth in the wireless telecommunications market has created a strong demand
for leading-edge EDA software to handle the complex design of RF/mixed-signal (MS) circuits. While
traditional circuit simulators (such as Virtuoso ® Spectre ® Circuit Simulator) are suitable for accurate
simulation of RF/MS building blocks, they are often too slow to simulate an entire circuit such as RF PLL or
ADC/DAC, not to mention the RF/MS SoC, which often contains on-chip power regulators, RF/MS blocks,
and large digital blocks.
Virtuoso UltraSim Full-chip Simulator is a hierarchical FastSPICE simulator, well known for its capability in
simulating multimillion transistor memory circuits. Virtuoso UltraSim's architecture and solver are also
designed to target large MS circuits with working frequency from DC to multi-GHz. A key factor in
simulating RF/MS circuits is the support of complex device models arising from advanced BiCMOS and
deep submicron processes. Equally important is the support of HDL models (such as Verilog-A), which are
often used to model components such as varactors and VCOs. Not only does Virtuoso UltraSim have the
most extensive and updated model support, but it is also fully compatible with the Virtuoso Spectre
simulator, as they use the same models. This automatically guarantees the consistency in the simulation
results between the two simulators.
The newly implemented AMR (analog multi-rate) simulation mode uses a novel numerical method to
simulate circuit blocks with very different time steps, resulting in much faster and more robust simulation.
Though most of the simulation options can be applied locally to allow tradeoffs between speed and
accuracy for individual blocks, AMR mode provides users with a FastSPICE simulation mode that still works
with simple options; other simulators often require the setting of many local options, which is not always
easy to do. For RF circuits, accurate simulation is impossible without considering all the RC parasitic.
Virtuoso UltraSim's frequency-based RC reduction and RC stitching technologies greatly speed up postlayout
simulation of entire circuits with very little penalty on accuracy. This is especially important for
RF/MS circuits where inaccurate simulation often generates meaningless results.
2 INTRODUCTION
There is no doubt that the hottest area of customer IC development is in the design of complex systemon-chip
(SoC) products used in wireless applications such as cellular phones, WLAN, Bluetooth, and GPS. It
is not uncommon to find RF/MS SoC designs consisting of more than one million transistors. Although
98% of the million transistors are pure digital/memory blocks, the remaining 2% of circuitry — which can
be any kind of RF or analog blocks such as ADC/DAC and PLL — accounts for 40% of the design effort. A
conventional approach to simulate a mixed-signal circuit is to partition the design into digital and analog
portions. Each analog block is individually simulated using traditional SPICE simulators such as the
Virtuoso Spectre simulator or HSPICE, whereas logic simulators verify the digital blocks. Digital/analog cosimulators
such as Virtuoso AMS Designer verify the top-level connectivity and full-chip functionality. To
further speed up chip simulation, behavioral models may replace the analog blocks. Post-layout simulation
can only be done on some critical analog blocks due to the limited capacity of the SPICE simulator.
The rapid migration to nanometer technologies allows designers to push the working frequency into the
multi-GHz range and to pack even more transistors into a chip, but it also creates new challenges for the
simulation software. Very complex device models are used in RFCMOS, BiCMOS, SiGe, and SOI processes to
model the RF operation. More design houses are using internal proprietary device models rather than
standard models. Verilog-A models are used extensively to model components ranging from a simple
resistor up to a complex VCO or a digital controller. The simulator also needs to support special RF
elements such as lossy transmission lines, which may be modeled by S-parameters instead of lumped
elements. Due to the finer geometry and lower signal swing, noise and crosstalk can no longer be
neglected. IR drop on signal lines and power grids is becoming more critical as chips grow in size and
power. The use of on-chip power regulators creates tight coupling between all the blocks through the
power lines and even between the digital and analog blocks. Only full-chip transistor-level simulation can
reveal these kinds of problems. The high-frequency performance is limited by interconnect delay and RC
parasitic. Thus, chip-level post-layout simulation is the only way to guarantee meeting product
specifications on first-pass silicon. The extracted netlist can easily have multi-million components. The
simulator needs the capacity to handle the sheer size of a whole chip post-layout netlist, without
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compromising accuracy. More designers are relying on circuit simulators to check power consumption,
standby current, floating nodes, dc leakage path, and excessive voltage stress on the devices. Only fullchip
transistor-level simulation can provide the information needed to optimize timing, power, and
reliability in nanometer designs, and the peace of mind before cutting the million-dollar mask set.
3 VIRTUOSO ULTRASIM TECHNOLOGY ADVANTAGES
Virtuoso Spectre Circuit Simulator and HSPICE are examples of the first generation of SPICE simulation
products, which use compact analytical device models, a sparse matrix solver, and discretization
techniques to solve simultaneous nonlinear equations. They provide very accurate results for simulation of
analog circuits with up to 50K components (for acceptable simulation time). As circuit size and complexity
outgrew the capability of the first-generation SPICE software, the so-called FastSPICE simulators were
developed. The main ideas enabling this second-generation SPICE software to overcome the capacity and
speed limits of the older, more conventional products are: 1) partitioning; 2) multi-rate/event-driven
simulation; and 3) using table device models.
Partitioning is the process of dividing a design into different parts. Each partition is represented as a
matrix that can be solved separately during simulation. Instead of solving one huge matrix, secondgeneration
simulation software solves multiple smaller matrices. This can greatly reduce CPU time and
memory consumption. Another advantage of the partitioning approach is that each partition can be
simulated with different time steps. The time step for each partition is adjusted according to the
maximum signal frequency within each partition. This is known as multi-rate simulation. In fact, the
partitions are only evaluated when there are activities (events) at their inputs; otherwise they can be
skipped. This is the basis of event-driven simulation. Multi-rate and event-driven simulations result in a
tremendous speed improvement over conventional SPICE simulators. This is especially beneficial for
mixed-signal designs, which generally consist of circuit blocks with very different working frequencies.
SPICE simulators use complex analytical device models for MOSFETs and BJTs. These models are basically a
set of nonlinear equations that need to be solved at each time step. Since the evaluation of these
equations consumes a significant CPU time, second-generation simulation software uses simplified
equations and table models to speed up the computation of the I-V and Q-V characteristics. In general,
second-generation simulation software lets users select different levels of model abstraction according to
the required accuracy for each circuit block. For instance, the digital blocks use simplified digital table
models, whereas the analog blocks use more accurate analog table models.
The first two generations of simulation products are based on flat netlists. Virtuoso UltraSim is the thirdgeneration
SPICE simulator, which adds isomorphic hierarchical simulation techniques with adaptive
partitioning. The hierarchical simulation approach is based on the fact that most circuits have repetitive
structures. Digital designs use standard gates; memory circuits consist of millions of identical memory cells;
and mixed-signal designs have repetitive circuit blocks. For subcircuits that have the same topology and
stimuli, only a representative master needs to be simulated. This approach enables third-generation
products to simulate virtually any size of hierarchical circuit, while still providing SPICE-like accuracy. As
the stimuli change dynamically during simulation, partitions (and the representation of identical
partitions) can be split or re-grouped.
4 USING VIRTUOSO ULTRASIM FOR RF/MS SIMULATION
Virtuoso UltraSim is a fast, high-capacity simulator, but it is also a highly accurate SPICE simulator for
analog/RF circuits with working frequency from DC up to multi-GHz. Unlike other FastSPICE simulators,
which are basically digital solvers with an add-on analog simulation mode, Virtuoso UltraSim employs the
same SPICE simulation engine for the entire circuit and for all simulation modes. This guarantees “fulltime”
SPICE-like accuracy for all kinds of designs. For those circuits that do not require the highest
accuracy, users can trade off accuracy for speed. In general, the accuracy of SPICE simulation is determined
by the accuracy of the models and the simulation engine, which is, in turn, determined by tolerance
criteria used by the solver. Virtuoso UltraSim allows users to adjust each of them independently. The
simulation mode (sim_mode) specifies partitioning and the selection of device models, while the speed
option (speed) determines the simulation engine tolerance.
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SPICE (S) mode is the most conservative (accurate) mode and is equivalent to conventional SPICE software.
The entire circuit is simulated as a single partition using full analytical model equations. Analog (A) mode
uses no partitioning as S mode, but achieves a speed improvement of three to five times by using analog
table models. Mixed-signal (MS) mode shares the same table models with analog mode, but achieves
additional speed by partitioning the design. Analog multi-rate (AMR) mode is designed to achieve MS
mode speed with A mode accuracy and robustness. It uses the same analog table models as A mode and
employs a similar partitioning approach as MS mode, but the solver uses a novel technique to accurately
and efficiently handle the interaction between the partitions. Using AMR mode is as easy as using A mode
because local options are often not required. Digital accurate (DA) mode and digital fast (DF) mode both
use partitioning and digital table models. While the DF mode uses linear grounded device capacitance,
the DA mode takes into account the nonlinear capacitive coupling within the models. DF mode is
designed for the functional verification of digital and memory circuits. DA mode is intended for the
timing verification of the same applications. Once users have chosen the appropriate simulation mode for
their application, they can adjust the “speed dial” to control the accuracy of the simulation engine
according to the circuit requirement. The speed option can be set with a value from one to eight to
define the relative tolerance used by the solver. Both simulation modes and speed options (as well as
many other options) can be applied globally to the entire circuit or locally to each subcircuit (master), and
to each instance of the subcircuits or each device model.
Correct partitioning and selection of device models are the two key factors to achieve efficient and
accurate simulation of mixed-signal circuits. MS mode is the default simulation mode and is suitable for
most mixed-signal circuits. The default speed option (speed=5) is a good starting point for most circuits
and often can produce accurate enough results. These two options are normally set as the global options.
Next, local sim_mode and speed options can be set for individual blocks. For instance, sim_mode=da or df
and higher speed option (6-8) can be set for the digital and embedded memory blocks. Analog and RF
blocks must be simulated in A or S mode. In MS mode, Virtuoso UltraSim will automatically partition the
entire design according to the circuit topology and channel connectivity (devices that are channelconnected
are placed in one partition.)
While this algorithm works well for most circuits, in some situations there may be vigorous interactions
between different partitions, which can actually slow down simulation and/or degrade accuracy. The user
can correct this situation by setting the analog option. Set analog=2 or 3 will cause Virtuoso UltraSim to
increase the partition size. For example, with the default option of analog=1, a partition is large enough
to hold a simple ring oscillator. Setting analog=2 will increase the partition size to hold a complex
differential type ring oscillator. With analog=3 a partition can grow large enough to hold a small PLL. A
more direct way to control partitioning is to use the local sim_mode option. Assigning sim_mode=a or s to
a subcircuit ensures that the subcircuit will be simulated as a single partition (in addition to using analog
models). Sensitive analog blocks, which have feedback action or tight coupling between elements (such as
RF VCO, bandgap, op amp circuits, switched capacitor circuits, charge pumps, and virtually all RF blocks),
have to be simulated in A or S mode to ensure accuracy. S mode is mainly for comparison to conventional
SPICE products and is not needed for most circuits. Virtuoso UltraSim analog table models are accurate
enough for most applications. However, the following categories of circuits may require full analytical
models to achieve the required accuracy (very often a lower speed option is also required):
• High-precision analog circuits (bandgap circuits, high resolution ADC/DAC, op amp circuits)
• RF VCOs using LC tank circuits
• Some RF circuits
• Circuits consisting mainly of BJTs
• Circuits with MOSFETs operating in the sub-threshold region
PLL is probably the most important mixed-signal circuit that also consumes most of the simulator resource.
All PLLs share the same topology, but their complexity and working frequency can vary considerably. For
PLLs with fewer than 5K components and VCO frequency below 100MHz, it may be simpler to simulate
the entire loop in A mode to obtain robust results. Usually no local option is required. Typical simulation
time from start up to lock acquisition is about a half day to one full day. For very complex PLLs, RF PLLs, or
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PLLs with post-layout netlists, MS mode should be used to speed up simulation. If the PLL fails to operate
properly, users can try the global option analog=2 or 3. A common problem is that the VCO fails to start,
in which case the following local options for the VCO may need to be set:
• sim_mode=a
• speed=3 or 4
• method=trap or gear2
Some VCO circuits with lower loop gain might need a kick start. For RF VCOs with inductors, a common
trick is to connect a transient current source (1mA, 0.1ns duration) in parallel with each inductor. For ring
oscillator type VCOs, it can be done by forcing one or two of the internal nodes to high/low at the onset
of simulation (by using an initial condition statement).
For PLLs with postlayout netlists, the user may need to turn on RC reduction using the postl option.
Virtuoso UltraSim supports all major post-layout netlist formats such as SPEF, DSPF, and DPF. Its RC
backannotation approach is optimized to stitch the RC parasitic of the flat DSPF/SPEF data into the
hierarchical schematic netlist. Virtuoso UltraSim will also compact the RC networks while preserving their
electrical behavior. The user can specify five levels of RC reduction:
• No RC reduction (postl=0)
• Conservative RC reduction (postl=1)
• Moderate RC reduction (postl=2)
• Liberal RC reduction (postl=3)
• Keep parasitic Cs only, short all parasitic Rs (postl=4)
Virtuoso UltraSim's superior RC reduction techniques make it possible to reduce the number of RCs by up
to 90% while still producing accurate results. Since accuracy is of paramount importance for RF/MS
simulation, the user should choose post=1 or 2 for post-layout simulation. It should be noted that the
current implementation of RC reduction algorithm does not support reduction of extracted inductance.
For those extracted netlists containing many parasitic inductances, a solution is to use the lshort option to
eliminate most of the small inductance and only keep the larger ones. Then the postl option can be
applied to enable RC reduction.
Many mixed-signal and memory circuits consist of on-chip voltage regulators and charge pumps.
Simulating these circuits in MS mode often produces unsatisfactory results due to the tight interaction
between partitions through the internal power lines. Simulation in A mode will be too slow due to the
size of the circuit. Virtuoso UltraSim AMR mode is designed for these applications. AMR mode uses a
novel solver technique to handle the interaction between partitions and should be used for the following
categories of circuits:
• Circuits using internal voltage generators or charge pumps
• Power up simulation of analog and mixed-signal circuits
• Smaller- and medium-sized designs with inductors or resistors in the power nets
• Sensitive or high-precision designs with more than 30K devices
• Circuits with excessive interaction between partitions, but are too large to be handled by A mode
Virtuoso UltraSim is the only FastSPICE simulator that supports fast envelope following transient
simulation. Many RF circuits process signals generated with high-frequency carriers modulated by lowfrequency
baseband signals using various schemes such as amplitude, phase, and frequency modulation.
Conventional transient analysis is inefficient for these circuits due to the widely spread signal frequencies,
which require the time duration to follow the slow modulating signals, but the time steps depend on the
fast carrier signals, resulting in a prohibitively large number of time steps. Traditional envelope-following
methods suffer from the bottleneck of limited capacity. Virtuoso UltraSim employs a novel approach for
large-capacity, fast envelope following analysis based on the pseudo-spectral method, which approximates
signals with high-order polynomials or Harmonic basis functions to achieve spectral accuracy like
Harmonic Balance.
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In this technique, the signal is expressed as the sum of an envelope part and a high-frequency part.
Taking advantage of the slow change of the envelope, only one time point in a period of the fast carrier
signal has to be solved. Additional techniques are applied to ensure convergence and accuracy. The new
approach shows speed improvement up to 30 times over conventional transient analysis and is still
effective for large-scale RF circuits.
Finally, Virtuoso UltraSim supports virtually all the elements and device models accepted by Virtuoso
Spectre Circuit Simulator and HSPICE. Virtuoso UltraSim also supports Verilog-A as well as Spectre HDL
languages; both are widely used in device models and circuit behavioral models for mixed-signal
simulation. Virtuoso UltraSim and Virtuoso Spectre simulators share the same source codes for the
Verilog-A engine and device models (through CMI), which guarantees full compatibility between the two
simulators. Users can even link their own compiled device models into Virtuoso UltraSim in the same way
as they do with the Virtuoso Spectre simulator. This is gaining importance as more design houses are
relying on their own internal proprietary models. With this feature, they do not need to rely on the
simulator vendor to implement the new models. For mixed-signal simulation, Virtuoso UltraSim supports
both Virtuoso Spectre and HSPICE netlist formats, as well as structural Verilog ® netlists.
5 CASE STUDIES
PLL
The first circuit is a computer data bus interface controller. It consists of a receive path PLL (RXPLL), a
transmit path PLL (TXPLL), and large digital blocks (XDIGITAL) for data processing, as well as built-in-selftest
(BIST). The pre-layout HSPICE format netlist has 70K MOSFETs and 35K diodes. For both PLLs, the
input reference clock is 50MHz and the VCO is running at 1.25GHz. The following options are used for the
Virtuoso UltraSim simulation:
.usim_opt sim_mode=ms speed=5
.usim_opt sim_mode=a #TXPLL #RXPLL
.usim_opt sim_mode=df speed=6 dcut=1 XDIGITAL
The entire circuit is simulated in MS mode (sim_mode=ms) with default accuracy (speed=5). Setting
sim_mode=a for both PLLs forces Virtuoso UltraSim to place each PLL in a single partition. This
guarantees robust and accurate results without requiring any local options. This is an acceptable strategy
since each PLL contains fewer than 3K elements. The large digital block, XDIGIAL, is simulated in DF mode
with a slightly looser accuracy (speed=6). In addition, all the protection diodes in the logic gates are
removed from the netlist to speed up simulation (dcut=1). Running Virtuoso UltraSim on a 3GHz Linux
platform, the simulation time for a 25us transient (which covers start up to lock acquisition) is 44 hours.
Figure 1 shows the VCO clock (CKVCO), the reference (CKREF), and feedback (CKFB) signals at the phase
detector input after lock acquisition.
Figure 1: PLL simulation results
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RF PLL
The second circuit is an RF PLL for wireless applications. The Virtuoso Spectre pre-layout netlist consists of
21K MOSFETs, 400 BJTs, 50K diodes, and about 1K R/Cs. The reference clock is 26MHz and the LC type VCO
is running at 3.5GHz. The following options are used for the Virtuoso UltraSim simulation:
.usim_opt sim_mode=ms speed=5 analog=3
.usim_opt speed=4 method=gear2 IPLL.VCO
.usim_opt sim_mode=df IPLL.LOGIC
Since this PLL contains a large number of elements, the entire circuit has to be simulated in MS mode for
efficiency. The option analog=3 will cause Virtuoso UltraSim to use very conservative partitioning to avoid
breaking any feedback loop. Local options of speed=4 and method=gear2 are assigned to the VCO. Most
RF VCOs require the setting of trap or gear method and tighter solver tolerance for starting and
maintaining oscillation. The digital block is simulated with digital table models as set by the option
sim_mode=df. The simulation time for a 25us transient (from power up to lock acquisition) is 21 hours.
Figure 2 shows the VCO output signal (CKVCO), the reference (CKREF), and feedback (CKFB) signals at the
phase detector input after lock acquisition.
Figure 2: RF PLL simulation results
ADC
The third circuit is a high-speed 6-bit flash ADC with a data conversion rate of 2G-samples/sec. For such a
high working frequency, full-chip post-layout simulation is required to verify the operation of the design.
The Virtuoso Spectre netlist consists of 15K MOSFETs, 3K diodes, 80K extracted inductors, 150K extracted
resistors, and 640K extracted capacitors. The entire netlist has about 0.9M elements. The following option
is used for the Virtuoso UltraSim simulation:
.usim_opt sim_mode=ms speed=5 lshort=0.1n postl=1
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The circuit is simulated in MS mode with default accuracy. The option postl=1 enables first-level RC
reduction. Since the current RC reduction algorithm will not compact networks containing inductors, the
option lshort=0.1n is used to short out most of the inductors except the 700 largest ones with values
larger than 0.1nH. Because of the RC reduction, the total number of elements is reduced to 270K. The
simulation time for a 50ns transient is 10.4 hours. Figure 3 shows the analog input (Vin) and digital output
(Dout*) signals of the ADC. On the simulated waveforms, the effects of coupling from the high-frequency
clock on the digital outputs are evident.
Figure 3: ADC simulation results
VOLTAGE GENERATORS
The fourth circuit is the internal power supply system of a DRAM chip. The operation of DRAM cells
requires multiple supply voltages, which are different from the external supply voltage. In addition, a
negative substrate bias (vbb) is employed to reduce junction capacitance. These voltages are generated by
the on-chip charge pumps and voltage regulators. The pre-layout netlist of this example consists of 3K
MOSFETs and 3K R/Cs. On-chip voltage generators are good candidates for the AMR mode, which is
enabled with the following option:
.usim_opt sim_mode=amr
The following are simulation times for the AMR, A, and MS modes (speed=5 for all cases):
AMR mode: 25 min
A mode: 41 min
MS mode: 6 hr 20 min
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The inefficiency of MS mode is due to the feedback actions between different partitions. Specialized
partitioning options will soon be available in AMR mode to increase speed. Figure 4 shows the simulated
waveforms of the regulator outputs (vddh, vddl, vbb) and one of the charge pump clock signals (pumpclk).
Figure 4: Voltage generator simulation results
FAST ENVELOPE FOLLOWING SIMULATION
In this example, Virtuoso UltraSim's fast envelope following analysis will be demonstrated. This is a largescale
RF circuit consisting of 13K MOSFETs, 1K diodes, 100 BJTs, 100 inductors, 700 mutual inductors, 1.5K
control CMI elements, and 3.5K R/Cs. The carrier frequency is 1.8GHz. Using Virtuoso UltraSim's A mode, it
will take 59 minutes to finish simulation of a 1us transient. The simulation can be sped up by enabling the
following fast envelope following analysis options:
.usim_opt env_clockf=1.8G env_tstart=5ns env_maxnstep=40
.usim_opt sim_mode=a method=gear2
Env_clockf sets the carrier clock frequency while env_maxnstep sets the maximum number of carrier cycles
subjected to “envelope solve” (solving only one point per clock period). Using the new options, the same
simulation required only 11.5 minutes, achieving a six-fold speed up. Figure 5 compares the output
waveforms generated from the conventional transient simulation and the fast envelope following analysis.
Figure 5: Fast envelope following simulation results
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6 SUMMARY
Virtuoso UltraSim provides a powerful solution for accurate and efficient simulation of RF and mixedsignal
(MS) circuits. It enables circuit designers to consider nanometer effects that can only be revealed by
full-chip transistor-level simulation. The core of Virtuoso UltraSim is a true SPICE simulator, which provides
the foundation for accurate simulation of RF and analog circuits. Based on technologies such as
partitioning, multi-rate/event-driven methods, table models, and the hierarchical structure of most
circuits, Virtuoso UltraSim can simulate full-chip RF/MS circuits not possible with other conventional
simulators. The characteristics of RF circuits are dominated by the layout parasitic. Virtuoso UltraSim
parasitic backannotation and superior RC reduction technology allows post-layout simulation to be
performed on a chip level rather than on a block level. Virtuoso UltraSim is also easy to use.
Simulation mode and speed are the only two major options that can be applied globally or to individual
circuit blocks. The default MS mode is good for most mixed-signal designs, but some critical RF/analog
circuits have to be simulated in A mode to produce accurate results. Currently the new AMR mode is good
for power-up simulation and for designs with on-chip power generators or charge pumps. In the near
future, there will be a generic simulation mode that always works as robust as A and S modes, but with
FastSPICE speed.
Virtuoso UltraSim is the only FastSPICE simulator supporting fast envelope following transient simulation.
Simulation of RF circuits, which have a high-frequency carrier modulated by a low-frequency signal, can
be sped up by as much as 30 times. Virtuoso UltraSim has the best model support among all the
competitors in the industry. In addition, it also supports custom compiled models. With its superior
simulation capabilities, Virtuoso UltraSim is the simulator of choice for RF/MS SoC simulation.
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6114 03/05