Mixed Signal Assertion Based Verification - Cadence Design Systems

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SystemVerilog Cross Domain Connectivity SystemVerilog testbench driven methodology ◦ 3 classes of connectivity supported: Data and net types between Verilog‐2001 and Verilog‐AMS objects SV Real Variable to Verilog‐AMS Electrical –insertion of E2R connect module SV Real Variable to Verilog‐AMS WReal – direct connection by `include "discipline.h" module ams_src(e); output e; electrical e; analog V(e) 0.5; endsequence sva_opcheck1 : assert property (@(posedge clk) S1); `include "discipline.h" module ams_dest(w); input w; wreal w; initial $display("%M: %f", w); endmodule November 12, 2010 Cadence Confidential: Cadence Internal Use Only 15 November 12, 2010 Cadence Confidential: Cadence Internal Use Only 16 11/12/2010 8
Leveraging Assertions In an ADC Capturing p gSpecification p of Sequential q Behavior ADC’s, DAC’s, Switch Cap Filters, Serdes good candidates ◦ Specification of circuits contains sequential behavior ADC example the following behavior is verified ◦ Integrator behavior ◦ Comparator Operations ◦ Loop Stability Fundamentals ADC Architecture Representation Sigma Delta Architecture ◦ Modulator and Filter Modulator with Integrator Feedback Filter 11/12/2010 9
Page 1 and 2: www.armtechcon.com Agenda November
Page 3 and 4: Analog Effects Into Logic Verificat
Page 5 and 6: Spe c Introduction to Assertion Bas
Page 7: PSL Mixed Signal Assertions PSL is
Page 11: ADC PSL Viewing the Results Asserti

Mixed Signal Assertion Based Verification - Cadence Design Systems

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