Mixed Signal Assertion Based Verification - Cadence Design Systems

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Introduction to Assertion Based
Verification
•Simulation
•HW HW Acceleration
•Emulation
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Top-level Integrated Design
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Integrated Blocks
•Formal Analysis
ABV Debugging
•Formal Analysis
•Hybrid
•Simulation
Improve documentation
Improved observability
◦ Id Identifies tifi errors where h th they
take place instead of at the
outputs
◦ Monitors behavior for all
vectors
Improved controllability
Improved coverage
ABV enables a comprehensive verification approach
Select Assertion -> Select Waveform Icon
Location of failures are
highlighted in red
Verification starts sooner
November 12, 2010 Cadence
Confidential: Cadence Internal Use
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November 12, 2010 Cadence
Confidential: Cadence Internal Use
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11/12/2010
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