Damage formation and annealing studies of low energy ion implants ...

To continue to improve devices there is a growing need to better understand all
the mechanisms involved to fully exploit all the possibilities for improvement. The
work in this thesis is concerned with understanding some of the mechanisms involved.
There is also a growing need to introduce novel methods of improving device
performance. Advanced structures have to be considered as well introducing new ways
to improve performance using the current device structure (5, 14, 32). The introduction
of strain in devices is now actively pursued as one way to improve performance. In
strained Si there can be higher carrier mobility (18). Devices may be created either
through using strained SiGe or by using highly stressed overlayer films that are
selectively formed over the NMOS and PMOS regions (14). Tensile films are used for
NMOS and compressive ones for PMOS.
Another method to improve the operation of the transistor has been the
introduction into volume production, within the last two years, of devices created on
silicon on insulator (SOI) wafers for an improvement in the area of device latch – up,
i.e. better isolation of the devices from the bulk substrate so that capacitance effects do
not cause one transistor to interfere with the operation of surrounding transistors (3).
Partially depleted devices have a similar construction to the standard CMOS devices,
the source and drain do not extend to the depth of the buried oxide layer. These devices
are already in production. Fully depleted devices are formed on narrow Si layers and the
source and drain extend down to the buried oxide. A move to this sort of transistor is
expected within a few years (9, 13). Further benefits and differences of SOI transistors
are beyond the scope of this thesis. Because of the growing importance of SOI
substrates a description of work comparing the regrowth behaviour of SOI and bulk Si
substrates is included in Chapter 6 of this thesis.
1.3 Ion implantation
Ion implantation is carried out in an ion implanter in which dopant atoms are
ionised in an ion source plasma. Positively charged ions are extracted from the source
and accelerated in an electrostatic lens that forms them into a beam, mass analysed in a
magnetic field (and occasionally focused in electric fields), and accelerated or
decelerated, before impinging on the wafer (5). Since all practical implant energies
exceed the threshold for lattice atom displacement, the process of ion implantation
inevitably produces damage to the Si crystal lattice structure through collisions of the
dopant ions with the Si atoms and the accommodation of the implanted ions within the
matrix (19).
8