Damage formation and annealing studies of low energy ion implants ...

Figure 1.3 Roadmap for device shrinkage at AMD with XTEM of test structures.
Modified from (9).
It has been noted that the rate of improvement cannot continue by merely
reduced scaling alone due to the existence of fundamental material limits. For example,
the gate oxide and Lg scaling is reaching its limit, because for much thinner oxides, gate
oxide leakage current would dominate and high-k materials are not yet mature enough
for high volume manufacturing (14, 15). The oxide layers in production have a
thickness of around 1.2 nm but by the time scaling has reduced the required oxide layer
to a thickness of 0.7 nm, this will correspond to just two atomic layers and is probably
the ultimate manufacturing limit of bulk silicon oxide (32). The limit in downscaling
must ultimately be related to the spacing between the atoms in the Si crystal, i.e.
approximately 0.3 nm (33). In much the same way, with continued downscaling a point
will be reached where there will so few dopant atoms in the channel region (down to as
few as 100), that any small statistical variations in the number would have dramatic
consequences on the device operation. It is not known if the number of dopant atoms
could be controlled with the required accuracy (26).
There is a complicated relationship between many transistor parameters. It is
therefore extremely important to carefully optimise all parameters for the best overall
performance and reliability of the device and the production costs (14, 16, 17). For
example it has been observed that simply reducing the SDE junction depth does not
specifically lead to an improvement in overall device performance. Variation in Xj did
not produce an observable variation in the threshold voltage characteristics (16).
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