Damage formation and annealing studies of low energy ion implants ...
Damage formation and annealing studies of low energy ion implants ... Damage formation and annealing studies of low energy ion implants ...
Figure 1.3 Roadmap for device shrinkage at AMD with XTEM of test structures. Modified from (9). It has been noted that the rate of improvement cannot continue by merely reduced scaling alone due to the existence of fundamental material limits. For example, the gate oxide and Lg scaling is reaching its limit, because for much thinner oxides, gate oxide leakage current would dominate and high-k materials are not yet mature enough for high volume manufacturing (14, 15). The oxide layers in production have a thickness of around 1.2 nm but by the time scaling has reduced the required oxide layer to a thickness of 0.7 nm, this will correspond to just two atomic layers and is probably the ultimate manufacturing limit of bulk silicon oxide (32). The limit in downscaling must ultimately be related to the spacing between the atoms in the Si crystal, i.e. approximately 0.3 nm (33). In much the same way, with continued downscaling a point will be reached where there will so few dopant atoms in the channel region (down to as few as 100), that any small statistical variations in the number would have dramatic consequences on the device operation. It is not known if the number of dopant atoms could be controlled with the required accuracy (26). There is a complicated relationship between many transistor parameters. It is therefore extremely important to carefully optimise all parameters for the best overall performance and reliability of the device and the production costs (14, 16, 17). For example it has been observed that simply reducing the SDE junction depth does not specifically lead to an improvement in overall device performance. Variation in Xj did not produce an observable variation in the threshold voltage characteristics (16). 7
To continue to improve devices there is a growing need to better understand all the mechanisms involved to fully exploit all the possibilities for improvement. The work in this thesis is concerned with understanding some of the mechanisms involved. There is also a growing need to introduce novel methods of improving device performance. Advanced structures have to be considered as well introducing new ways to improve performance using the current device structure (5, 14, 32). The introduction of strain in devices is now actively pursued as one way to improve performance. In strained Si there can be higher carrier mobility (18). Devices may be created either through using strained SiGe or by using highly stressed overlayer films that are selectively formed over the NMOS and PMOS regions (14). Tensile films are used for NMOS and compressive ones for PMOS. Another method to improve the operation of the transistor has been the introduction into volume production, within the last two years, of devices created on silicon on insulator (SOI) wafers for an improvement in the area of device latch – up, i.e. better isolation of the devices from the bulk substrate so that capacitance effects do not cause one transistor to interfere with the operation of surrounding transistors (3). Partially depleted devices have a similar construction to the standard CMOS devices, the source and drain do not extend to the depth of the buried oxide layer. These devices are already in production. Fully depleted devices are formed on narrow Si layers and the source and drain extend down to the buried oxide. A move to this sort of transistor is expected within a few years (9, 13). Further benefits and differences of SOI transistors are beyond the scope of this thesis. Because of the growing importance of SOI substrates a description of work comparing the regrowth behaviour of SOI and bulk Si substrates is included in Chapter 6 of this thesis. 1.3 Ion implantation Ion implantation is carried out in an ion implanter in which dopant atoms are ionised in an ion source plasma. Positively charged ions are extracted from the source and accelerated in an electrostatic lens that forms them into a beam, mass analysed in a magnetic field (and occasionally focused in electric fields), and accelerated or decelerated, before impinging on the wafer (5). Since all practical implant energies exceed the threshold for lattice atom displacement, the process of ion implantation inevitably produces damage to the Si crystal lattice structure through collisions of the dopant ions with the Si atoms and the accommodation of the implanted ions within the matrix (19). 8
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Figure 1.3 Roadmap for device shrinkage at AMD with XTEM <strong>of</strong> test structures.<br />
Modified from (9).<br />
It has been noted that the rate <strong>of</strong> improvement cannot continue by merely<br />
reduced scaling alone due to the existence <strong>of</strong> fundamental material limits. For example,<br />
the gate oxide <strong>and</strong> Lg scaling is reaching its limit, because for much thinner oxides, gate<br />
oxide leakage current would dominate <strong>and</strong> high-k materials are not yet mature enough<br />
for high volume manufacturing (14, 15). The oxide layers in product<strong>ion</strong> have a<br />
thickness <strong>of</strong> around 1.2 nm but by the time scaling has reduced the required oxide layer<br />
to a thickness <strong>of</strong> 0.7 nm, this will correspond to just two atomic layers <strong>and</strong> is probably<br />
the ultimate manufacturing limit <strong>of</strong> bulk silicon oxide (32). The limit in downscaling<br />
must ultimately be related to the spacing between the atoms in the Si crystal, i.e.<br />
approximately 0.3 nm (33). In much the same way, with continued downscaling a point<br />
will be reached where there will so few dopant atoms in the channel reg<strong>ion</strong> (down to as<br />
few as 100), that any small statistical variat<strong>ion</strong>s in the number would have dramatic<br />
consequences on the device operat<strong>ion</strong>. It is not known if the number <strong>of</strong> dopant atoms<br />
could be controlled with the required accuracy (26).<br />
There is a complicated relat<strong>ion</strong>ship between many transistor parameters. It is<br />
therefore extremely important to carefully optimise all parameters for the best overall<br />
performance <strong>and</strong> reliability <strong>of</strong> the device <strong>and</strong> the product<strong>ion</strong> costs (14, 16, 17). For<br />
example it has been observed that simply reducing the SDE junct<strong>ion</strong> depth does not<br />
specifically lead to an improvement in overall device performance. Variat<strong>ion</strong> in Xj did<br />
not produce an observable variat<strong>ion</strong> in the threshold voltage characteristics (16).<br />
7