Damage formation and annealing studies of low energy ion implants ...

The enhancement mode transistor described is the type most commonly used. In
comparison a depletion mode transistor is engineered to normally conduct by creating a
thin doped layer of the same type as the source and drain underneath the gate. Applying
a gate voltage which is opposite in polarity to the voltage applied in enhancement mode
devices makes conduction stop. In all cases silicide or metal contacts allow the
terminals to be connected to other devices by metal interconnects. The above is in fact a
very simplified description of a transistor. Many implantations and processing steps are
required to make a device.
Figure 1.1 a) Schematic of a MOS transistor. b) XTEM image of an AMD
optimised transistor with a gate length of 35 nm, modified from (16).
In CMOS both NMOS and PMOS transistors are manufactured on a single
wafer by first forming wells doped oppositely to the wafer in which to build the
transistor in. Usually an n-type well is formed in a p-type wafer to form a PMOS
device. The main advantage of CMOS over NMOS and bipolar technology is the much
smaller power dissipation. Theoretically a CMOS circuit has almost no static power
dissipation and power is only dissipated when the circuit switches (3).
Two important physical parameters that affect transistor performance are the
gate length Lg, and the SDE junction depth, Xj. The gate length has an important
bearing on the speed of operation of a device, as the velocity of electron motion in Si is
limited, therefore the time for the current to travel the distance from source to drain
depends on the distance of travel. The junction depth has to be related to the gate length,
as discussed below. From an analysis point of view Xj is often somewhat arbitrarily
taken to be the depth where the concentration of dopants in the extension is 1E18 cm -3 .
3
Gate
Extensions