Damage formation and annealing studies of low energy ion implants ...

terminal (Vg), current cannot flow from the gate because of the insulating layer.
(However in reality some gate leakage can occur.) The electric field due to an applied
voltage, affects electrons and/or holes in channel region.
In the absence of a bias voltage on the gate, relative to the substrate (which is
usually at earth potential along with the source), the source and drain regions form two
back to back semiconductor junction diodes. No current can flow from the source to
drain irrespective of the voltage applied between them and the transistor is termed to be
in the “off” state (although some reverse gate leakage current can occur in this state).
An NMOS transistor has an n-doped source and drain and is p-doped under the gate.
Applying a positive voltage to the gate will create an n-channel inversion layer, by first
repelling holes and then attracting electrons into that region. The n – type source and
drain are then connected by a surface n – channel, enabling the flow of current from the
source to drain, if a voltage is applied to the drain (VD). Electrons form the majority
charge carriers. The opposite is true for PMOS transistors, which consist of p – type
source and drains and an n – doped channel. When a negative voltage is applied to the
gate, a p – channel inversion layer is formed in which holes form the majority charge
carriers (2-7).
The threshold voltage (Vt) is the gate voltage for which the channel region
becomes strongly inverted and current can start to flow from source to drain. In this
state the transistor is said to be “on” (2-7). The threshold voltage (Vt) is of great
importance and can be adjusted by one or more threshold adjust implants in the device.
A threshold voltage adjust implant places dopants just under the gate oxide (8).
The gate voltage determines the width of the conducting channel and hence the
current that can flow in the channel from source to drain can be modulated by varying
the gate voltage (2-7). For increasing drain voltages, the drain current quickly reaches a
saturated point determined by the gate voltage.
The source / drain extensions (SDE) extend underneath the gate and consist of
more lightly doped regions than the source and drain. They provide a gradual dopant
concentration gradient between the S/D and the channel region which reduces the
maximum electric field and hence reduces the threshold voltage (5). Smaller electric
fields are required in order to avoid hot carrier effects. A large electric field can
accelerate the carriers, usually electrons because of their higher mobility, to high
energies. The energetic, termed hot, electrons can be accelerated into the gate oxide.
Excess charge building in the oxide will change the device operating characteristics
over time (7).
2