Damage formation and annealing studies of low energy ion implants ...

Chapter 1 Introduction
1.1 Introduction
Low energy ion implantation is a key processing step for the production of
integrated circuits (IC’s) in ultra large scale integrated technology (ULSI). It is the most
widely used method for introducing dopant atoms into silicon wafers to produce
electrically active n – type and p – type doped regions in complementary metal oxide
semiconductor (CMOS) transistors, as well as other types of devices. The main reason
for this is the technique’s ability to control the depth and dose of the implanted dopant
atoms with the necessary level of accuracy and reproducibility for volume production
(1).
An unavoidable consequence of energetic ion bombardment is the displacement
of lattice atoms. The work described in this thesis is a study of the behaviour of the
damage growth and dopant accumulation during ultra low energy implantation, as well
as damage dissolution and dopant redistribution effects during annealing. Studies were
carried out in collaboration with Advanced Micro Devices (AMD), the world’s second
largest processor manufacturer. The implantation conditions studied in this thesis are
relevant to current and future device production. A brief description of transistors and
the current state of the technology is made within this introduction to set the context for
the later work.
1.2 CMOS Devices
The most important transistors in IC’s are metal oxide semiconductor field effect
transistors (MOSFET) (2). These can be either n-channel (NMOS) or p-channel
(PMOS) transistors. CMOS, which dominates IC technology, utilises both NMOS and
PMOS transistors. A schematic of an enhancement mode NMOS or PMOS transistor is
shown in Figure 1.1a). The physical structure of both transistors is essentially the same
and they consist of two highly doped regions, the source and drain, which are oppositely
doped with respect to the surrounding region. The Fermi level (the energy level at
which the probability of occupation by an electron is 0.5 (7)) has to be continuous
across a junction of n and p regions at equilibrium, therefore electrons and holes migrate
across the junction, creating positive and negative space charge regions which forms a
depletion region at the junction. Between the source and drain is the channel. A
polysilicon gate terminal placed over the channel is separated from the channel by an
insulating SiO2 layer. In an ideal device, when a bias voltage is applied to the gate
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