Damage formation and annealing studies of low energy ion implants ...

and the 2D picture in Figure 6.31b). It is clear that for the case of 60 nm SOI some Xe
and energetic interstitials will reach the BOX.
a)
b)
TRIM A.U.
1
0.1
0.01
40 keV Xe TRIM profiles
Amorphous thickness
Xe ions
Si vacancies
Si interstitials
0 100 200 300 400 500 600 700 800 900 1000
Depth / Ang
BOX interface
Figure 6.31 a) TRIM results for a 40 keV Xe implant, together
with the Si vacancy and interstitial depth profiles. b) Pictorial
representation of the calculation.
TRIM results suggest that for the 88 nm and 100 nm SOI wafers the recoiled
interstitials will not reach the BOX, but could be within ~ 20 nm. However interstitials
produced in the collision cascade are mobile at room temperature and may migrate to
and be trapped at the interface, as seen at the surface (14, chapter 5). Excess interstitials
at the end of the range of the implant will have a higher chance to be trapped at the
BOX than at the surface.
The following model is tentatively put forward. The model assumes that due to
the capture of interstitials from the cascade dendrites extending from the main collision
cascade envelope towards the SOI interface may be captured in aggregates at the BOX
interface. It also assumes that the dendrite region means the amorphous / crystal
interface makes the surface form a less than perfect seed for the SPER. Hence locally at
these dendrites SPER is retarded and the regrowth interface instead of being flat as in
168
1E-3
1E-4
1E-5
TRIM A.U.
Xe (A.U.)