Enabler II-G Assiste GPS Integration Guide - Farnell
Enabler II-G Assiste GPS Integration Guide - Farnell
Enabler II-G Assiste GPS Integration Guide - Farnell
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Enfora <strong>Enabler</strong> <strong>II</strong>I-G<br />
Modem <strong>Integration</strong> <strong>Guide</strong><br />
4.6.1.4. Vbat Input<br />
The <strong>Enabler</strong> Vbat input can have a relative high current draw that can fluctuate rapidly,<br />
especially when transmitting at max power and burst mode. The Vbat interface must be<br />
designed to provide the required instantaneous voltage and current with minimal voltage<br />
droop. This includes both sufficient bulk decoupling capacitance as well as adequate layout<br />
provisions.<br />
When laying out the connections to the <strong>Enabler</strong> interface connector, it is tempting to use<br />
traces of the same width as the connector pins. However, this is a very compact connector<br />
and traces of that width will not have sufficient copper. Similar to the discussion on thermal<br />
relief, the use of narrow traces to connect the Vbat pins to the source voltage can act like a<br />
high impedance and cause a significant voltage droop when higher currents are required as<br />
shown in Figure 4.<br />
Figure 4 - Example of Vbat Voltage Droop<br />
If the Vbat drops too low, the <strong>Enabler</strong> modules will reset. To minimize the trace loss, it is<br />
suggested to use a larger trace that spans several pins as shown in Figure 5. Any concern<br />
about solderability can be mitigated by using solder mask with cutouts for the individual pins<br />
as shown by the blue lines in the figure. The layout should provide sufficient trace width over<br />
the entire trace from the Enable modules all the way to the source of the Vbat voltage. Any<br />
transitions between layers for this trace should utilize multiple vias.<br />
Since even the best layout will have some impedance from the source to the <strong>Enabler</strong> module,<br />
sufficient bulk decoupling capacitance is required at the Vbat input to the <strong>Enabler</strong> module. It<br />
is suggested to use at least two 1000 uF, low ESR, tantalum capacitors located very close to<br />
the <strong>Enabler</strong> interface connector Vbat pins. Any thermal relief used on these capacitors<br />
should comply with the information given above in order to provide the lowest impedance<br />
possible. The grounding of these capacitors is critical. Therefore, it should be a<br />
GSM0308PB001 17 Version 1.03– 7/17/2007